Systems and methods for performing instructions to convert to 16-bit floating-point format
Disclosed embodiments relate to systems and methods for performing instructions to convert to 16-bit floating-point format. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of a first source vector comprising N single-precision elements, and a destination vector comprising at least N 16-bit floating-point elements, the opcode to indicate execution circuitry is to convert each of the elements of the specified source vector to 16-bit floating-point, the conversion to include truncation and rounding, as necessary, and to store each converted element into a corresponding location of the specified destination vector, decode circuitry to decode the fetched instruction, and execution circuitry to respond to the decoded instruction as specified by the opcode.
1. A chip comprising:
a plurality of memory controllers;
a level-two (L2) cache memory coupled to the plurality of memory controllers;
a processor coupled to the plurality of memory controllers, and coupled to the L2 cache memory, the processor having a plurality of cores, including a core that, in response to a format conversion instruction having a first source operand including a first 32-bit single-precision floating point data element, and a second source operand including a second 32-bit single-precision floating point data element, is to:
convert the first 32-bit single-precision floating point data element to a first 16-bit floating point data element, wherein, when the first 32-bit single-precision floating point data element is a normal data element, conversion is to be performed according to a rounding mode specified by the format conversion instruction, and the first 16-bit floating point data element is to have a sign bit, an 8-bit exponent, seven explicit mantissa bits, and one implicit mantissa bit, and wherein, when the first 32-bit single-precision floating point data element is a not-a-number (NaN) data element, the first 16-bit floating point data element is to have a mantissa with a most significant bit set to one;
convert the second 32-bit single-precision floating point data element to a second 16-bit floating point data element, wherein, when the second 32-bit single-precision floating point data element is a normal data element, conversion is to be performed according to the rounding mode, and the second 16-bit floating point data element is to have a sign bit, an 8-bit exponent, seven explicit mantissa bits, and one implicit mantissa bit, and wherein when the second 32-bit single-precision floating point data element is a NaN data element, the second 16-bit floating point data element is to have a mantissa with a most significant bit set to one; and
store the first 16-bit floating point data element in a lower order half of a destination register and the second 16-bit floating point data element in a higher order half of the destination register;
an interconnect coupled to the processor; and
a bus controller coupled to the processor.
2. The chip of claim 1 , wherein the first and second 16-bit floating point data elements are first and second BF16 format data elements.
3. The chip of claim 1 , further comprising an instruction converter to convert the format conversion instruction into one or more instructions of a different instruction set executable by the core.
4. The chip of claim 1 , wherein the plurality of cores comprise graphics cores.
5. The chip of claim 1 , wherein the plurality of cores are heterogeneous.
6. The chip of claim 1 , wherein the processor further comprises:
a first register to store the first 32-bit single-precision floating point data element; and
a second register to store the second 32-bit single-precision floating point data element.
7. The chip of claim 1 , wherein the processor includes:
an additional cache memory; and
a register file.
8. A chip comprising:
a plurality of memory controllers;
a level-two (L2) cache memory coupled to the plurality of memory controllers;
a processor coupled to the plurality of memory controllers, and coupled to the L2 cache memory, the processor having a plurality of cores, including a core that, in response to a format conversion instruction having a first source operand including a first 32-bit single-precision floating point data element, and a second source operand including a second 32-bit single-precision floating point data element, is to:
upon a determination the first 32-bit single-precision floating point data element is a not-a-number (NaN) data element, convert the first 32-bit single-precision floating point data element to a first 16-bit floating point data element having a mantissa with a most significant bit set to one;
upon a determination the second 32-bit single-precision floating point data element is a normal data element, convert the second 32-bit single-precision floating point data element to a second 16-bit floating point data element according to a rounding mode specified by the format conversion instruction, wherein the second 16-bit floating point data element has a sign bit, an 8-bit exponent, seven explicit mantissa bits, and one implicit mantissa bit; and
store the first 16-bit floating point data element in a lower order half of a destination register and the second 16-bit floating point data element in a higher order half of the destination register;
an interconnect coupled to the processor; and
a bus controller coupled to the processor.
9. The chip of claim 8 , wherein the second 16-bit floating point data element is a BF16 format value.
10. The chip of claim 8 , further comprising an instruction converter to convert the format conversion instruction into one or more instructions of a different instruction set executable by the core.
11. The chip of claim 8 , wherein the plurality of cores comprise graphics cores.
12. The chip of claim 8 , wherein the plurality of cores are heterogeneous.
13. The chip of claim 8 , wherein the processor further comprises:
a first register to store the first 32-bit single-precision floating point data element; and
a second register to store the second 32-bit single-precision floating point data element.
14. The chip of claim 8 , wherein the processor includes:
an additional cache memory; and
a register file.
15. An apparatus comprising:
a memory controller;
a level-two (L2) cache memory coupled to the memory controller;
a plurality of cores coupled to the memory controller, and coupled to the L2 cache memory, the plurality of cores including a core that, in response to a format conversion instruction having a first source operand including a first 32-bit single-precision floating point data element, and a second source operand including a second 32-bit single-precision floating point data element, is to:
convert the first 32-bit single-precision floating point data element to a first 16-bit floating point data element, wherein, when the first 32-bit single-precision floating point data element is of a first type, conversion is to be performed according to a rounding mode specified by the format conversion instruction, and the first 16-bit floating point data element is to have a sign bit, an 8-bit exponent, seven explicit mantissa bits, and one implicit mantissa bit, and wherein, when the first 32-bit single-precision floating point data element is of a second type different from the first type, the first 16-bit floating point data element is to have a mantissa with a most significant bit set to one;
convert the second 32-bit single-precision floating point data element to a second 16-bit floating point data element, wherein, when the second 32-bit single-precision floating point data element is of the first type, conversion is to be performed according to the rounding mode, and the second 16-bit floating point data element is to have a sign bit, an 8-bit exponent, seven explicit mantissa bits, and one implicit mantissa bit, and wherein when the second 32-bit single-precision floating point data element is of the second type, the second 16-bit floating point data element is to have a mantissa with a most significant bit set to one; and
store the first 16-bit floating point data element in a lower order half of a destination register and the second 16-bit floating point data element in a higher order half of the destination register;
an interconnect coupled to the plurality of cores; and
a bus controller coupled to the plurality of cores.
16. The apparatus of claim 15 , wherein the first and second 16-bit floating point data elements are first and second BF16 format data elements.
17. The apparatus of claim 15 , further comprising an instruction converter to convert the format conversion instruction into one or more instructions of a different instruction set executable by the core.
18. The apparatus of claim 15 , wherein the plurality of cores comprise graphics cores.
19. The apparatus of claim 15 , wherein the plurality of cores are heterogeneous.
20. The apparatus of claim 15 , further comprising:
a first register to store the first 32-bit single-precision floating point data element; and
a second register to store the second 32-bit single-precision floating point data element.
21. The apparatus of claim 15 , further comprising:
an additional cache memory; and
a register file.
22. The apparatus of claim 15 , wherein the first type is a normal floating point value and the second type is a not-a-number type.
23. A system comprising:
a system memory; and
a processor coupled to the system memory, the processor comprising:
a decode unit to decode a format conversion instruction, the format conversion instruction to indicate a location of a first source operand, a location of a second source operand, a destination register, a writemask register, and a type of masking, the first source operand to include a first plurality of 32-bit single-precision floating point data elements, the second source operand to include a second plurality of 32-bit single-precision floating point data elements, the writemask register to store a plurality of mask bits each corresponding to a data element position in the destination register, the type of masking to be either zeroing masking or merging masking; and
an execution unit coupled to the decode unit, the execution unit to execute the decoded format conversion instruction to:
for each of the first plurality of 32-bit single-precision floating point data elements that is of a first type, convert the 32-bit single-precision floating point data element to a 16-bit floating point data element using round to nearest even rounding behavior and store a result data element in a corresponding data element position in a first half of a result in the destination register if the mask bit corresponding to the data element position in the plurality of mask bits is set, and otherwise store a masked data element in the data element position, and
for each of the second plurality of 32-bit single-precision floating point data elements that is of the first type, convert the 32-bit single-precision floating point data element to a 16-bit floating point data element using round to nearest even rounding behavior and store a result data element in a corresponding data element position in a second half of the result in the destination register if the mask bit corresponding to the data element position in the plurality of mask bits is set, and otherwise store a masked data element in the data element position, the result data elements stored in the destination register to have a format that includes one sign bit, eight exponent bits, and seven explicit mantissa bits, the masked data element to be a zero value if the type of masking is zeroing masking and to be a preserved value if the type of masking is merging masking, wherein the first type is a normal number.
24. The system of claim 23 , wherein the format is a BF16 format, and wherein the system further comprises a mass storage device coupled to the processor.
25. The system of claim 23 , wherein the first half of the result is a lower order half of the result and the second half of the result is a higher order half of the result, and wherein the system further comprises a Peripheral Component Interconnect (PCI) Express bus coupled to the processor.
26. The system of claim 23 , wherein the location of the first source operand is a register location or a memory location, and wherein the first type excludes zero, denormal, infinity, and NaN, and wherein the system further comprises a communication device coupled to the processor.
27. The system of claim 23 , wherein the first source operand and the second source operand consist of a same number of bits, wherein the same number of bits is 128, 256, or 512 bits, and wherein the system further comprises a communication device coupled to the processor.
28. The system of claim 23 , wherein any denormal data elements in the first plurality of 32-bit single-precision floating point data elements and the second plurality of 32-bit single-precision floating point data elements are treated as zero values.
29. The system of claim 23 , wherein the round to nearest even rounding behavior is used irrespective of a rounding behavior specified by a control register.
30. The system of claim 23 , wherein the format includes one implicit mantissa bit, and wherein the system further comprises a mass storage device coupled to the processor.