IP Library › Granted Patent US 11,631,803
Granted Patent B2
US 11,631,803 · App. 17/134,485 · Granted Apr 18, 2023

Semiconductor device

Inventors: Hui-Lin Wang (Taipei, TW); Chun-Hsien Lin (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L43/02H01L27/222
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Quick Facts
Patent No.
US 11,631,803
App. No.
17/134,485
Granted
Apr 18, 2023
Kind
B2
Abstract

A semiconductor device for internet of things (IoT) device includes a substrate having an array region defined thereon and a ring of dummy pattern surrounding the array region. Preferably, the ring of dummy pattern includes a plurality of magnetic tunneling junctions (MTJs) and a ring of metal interconnect pattern overlapping the MTJs and surrounding the array region. The semiconductor device further includes a gap between the array region and the ring of dummy pattern.

Claims (15)

1. A semiconductor device for internet of things (IoT), comprising:

a substrate having an array region defined thereon;

a ring of dummy magnetic tunneling junction (MTJ) pattern surrounding the array region, wherein the ring of dummy pattern comprises:

magnetic tunneling junctions (MTJs); and

a ring of metal interconnect pattern overlapping the MTJs and surrounding the array region, wherein the MTJs comprise a first gap therebetween and an edge of the MTJs is aligned with an edge of the ring of metal interconnect pattern.

2. The semiconductor device for IoT of claim 1 , further comprising a gap between the array region and the ring of dummy pattern.

3. The semiconductor device for IoT of claim 1 , wherein the ring of metal interconnect pattern comprises:

a first metal interconnect pattern and a second metal interconnect pattern extending along a first direction; and

a third metal interconnect pattern and a fourth metal interconnect pattern extending along a second direction.

4. The semiconductor device for IoT of claim 3 , wherein the first metal interconnect pattern overlaps the third metal interconnect pattern at a first corner, the first metal interconnect pattern overlaps the fourth metal interconnect pattern at a second corner, the second metal interconnect pattern overlaps the third metal interconnect pattern at a third corner, and the second metal interconnect pattern overlaps the fourth metal interconnect pattern at a fourth corner.

5. The semiconductor device for IoT of claim 4 , wherein one of MTJs overlap the first corner.

6. The semiconductor device for IoT of claim 4 , wherein one of the MTJs overlap the second corner.

7. The semiconductor device for IoT of claim 4 , wherein one of the MTJs overlap the third corner.

8. The semiconductor device for IoT of claim 4 , wherein one of the MTJs overlap the fourth corner.

9. The semiconductor device for IoT of claim 1 , wherein each of the MTJs comprises a square or rectangle according to a top view.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 27, 2020
From: WANG, HUI-LIN; LIN, CHUN-HSIEN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 054750/0519 →
Priority Claims (1)
CN 202011354032.3 · Nov 27, 2020 · national
Continuity (1)
Related Publication 20220173306A1 · Jun 2, 2022
Cited By (1)
US 12,284,812