Operation device and operation method

1. An operation device, embodied in an electronic apparatus, comprising a quantizer circuit, a buffer circuit, a control circuit, a convolution core circuit and a multiply-add circuit; wherein,

the quantizer circuit receives first feature data and performs asymmetric uniform quantization on the first feature data to obtain and store in the buffer circuit second feature data, and receives a first weighting coefficient and performs symmetric uniform quantization on the first weighting coefficient to obtain and store in the buffer circuit a second weighting coefficient;

the convolution core circuit performs a convolution operation on the second feature data and the second weighting coefficient according to an instruction of the control circuit to obtain an initial operation result;

the multiply-add circuit performs a multiply-add operation on the initial operation result, an actual quantization scale factor and an actual bias value to obtain a final operation result; and

a trimming circuit, receiving the initial operation result having a first bit width, and trimming the initial operation result having the first width into an initial operation result having a second bit width;

wherein, the multiply-add circuit performs the multiply-add operation on the initial operation result having the second bit width, the actual quantization scale factor and the actual bias value to obtain the final operation result;

wherein, the first bit width is larger than the second bit width,

wherein the trimming circuit further receives the actual bias value having the first bit width, and trims the actual bias value having the first bit width into the actual bias value having the second bit width; the multiply-add circuit performs the multiply-add operation on the initial operation result having the second bit width, the actual quantization scale factor and the actual bias value having the second bit width to obtain the final operation result.

2. The operation device according to claim 1 , further comprising:

an offline calculation circuit, connected to the multiply-add circuit, offline calculating an initial bias value, calculated items generated by a quantization parameter zero, and the actual quantization scale factor, and merging the initial bias value and the calculated items generated by the quantization parameter zero to generate the actual bias value.

3. The operation device according to claim 2 , wherein the offline calculation circuit offline calculates by using single precision floating point.

4. An operation method performed by an electronic apparatus, wherein the electronic apparatus comprising a quantizer circuit, a buffer circuit, a control circuit, a convolution core circuit and a multiply-add circuit; the operation method comprising:

performing, by the quantizer circuit, asymmetric uniform quantization on first feature data to obtain and store in the buffer circuit second feature data;

performing, by the quantizer circuit, symmetric uniform quantization on a first weighting coefficient to obtain and store in the buffer circuit a second weighting coefficient;

performing, by the convolution core circuit, a convolution operation on the second feature data and the second weighting coefficient according to an instruction of the control circuit to obtain an initial operation result; and

performing, by the multiply-add circuit, a multiply-add operation on the initial operation result, an actual quantization scale factor and an actual bias value to obtain a final operation result,

wherein the step of performing the multiply-add operation on the initial operation result, the actual quantization scale factor and the actual bias value to obtain the final operation result comprises:

receiving, by a trimming circuit, the initial operation result having a first bit width, and trimming, by the trimming circuit, the initial operation result having the first width into an initial operation result having a second bit width;

performing, by the multiply-add circuit, the multiply-add operation on the initial operation result having the second bit width, the actual quantization scale factor and the actual bias value to obtain the final operation result;

wherein, the first bit width is larger than the second bit width, and

wherein the step of performing the multiply-add operation on the initial operation result having the second bit width, the actual quantization scale factor and the actual bias value to obtain the final operation result further comprises:

receiving, by the trimming circuit, the actual bias value having the first bit width, and trimming, by the trimming circuit, the actual bias value having the first bit width into the actual bias value having the second width; and

performing, by the multiply-add circuit, the multiply-add operation on the initial operation result having the second bit width, the actual quantization scale factor and the actual bias value having the second width to obtain the final operation result.

5. The operation method according to claim 4 , further comprising:

offline calculating an initial bias value, calculated items generated by a quantization parameter zero, and the actual quantization scale factor; and

merging the initial bias value and the calculated items generated by the quantization parameter zero to generate the actual bias value.

6. The operation method according to claim 5 , wherein the offline calculating is performed using single precision floating points.