Mouse chip easily updating firmware and operating method thereof
There is provided a control chip including a microcontroller unit (MCU), a bus arbiter, a first bus, a second bus, a void hardware, a cache controller, a flash controller and a flash memory, wherein the flash memory is recorded with a firmware. When the MCU does not receive an update instruction, the bus arbiter reads, according to a function command of the MCU, a function return value associated with the function command from the flash memory via the first bus, the cache controller and the flash controller. When the MCU receives the update instruction, the bus arbiter updates the firmware in the flash memory via the second bus and the flash controller, and the void hardware actively replies a void return value associated with the function command to the MCU to replace the function return value.
1. A mouse chip, comprising:
a flash memory, recorded with first firmware, and content of the flash memory being configured to operate a function called by the mouse chip to generate a function return value, wherein
the mouse chip is configured to
generate a function address of a function call,
perform address mapping on the function address to generate an operation address,
cache the function return value generated in the flash memory into a cache memory according to the operation address, and
hold mapping between cache addresses and flash addresses to accordingly cache the function return value at a corresponding flash address of the operation address and read the function return value in the cache memory via a first bus, or update the first firmware in the flash memory with update data via a second bus.
2. The mouse chip as claimed in claim 1 , wherein
upon not receiving an update instruction, the mouse chip is configured to read the function return value in the cache memory via the first bus, and
upon receiving the update instruction, the mouse chip is configured to send the update data via the second bus to update the first firmware in the flash memory.
3. The mouse chip as claimed in claim 2 , wherein
upon receiving the update instruction, the mouse chip is further configured to generate and reply a void return value conforming to a format of the function return value of the function to replace the function return value.
4. The mouse chip as claimed in claim 3 , wherein
the mouse chip further comprises multiple registers configured to record the function address and a function return address of the function, and
the mouse chip is further configured to change the function address and the function return address in the multiple registers upon receiving the update instruction.
5. The mouse chip as claimed in claim 4 , wherein the multiple registers comprise a program counter register and a link register.
6. The mouse chip as claimed in claim 2 , wherein the update instruction is generated by a mouse key or an external host.
7. The mouse chip as claimed in claim 1 , further comprising at least one of a read only memory and a random access memory, wherein the read only memory or the random access memory is embedded with second firmware.
8. The mouse chip as claimed in claim 7 , wherein
the first firmware is configured as a driver of a third party's integrated circuit, and
the second firmware is configured to calculate a mouse movement, and identify a mouse key click as well as a mouse roller rotation.
9. The mouse chip as claimed in claim 8 , wherein upon sending the update data via the second bus, the second firmware continuously calculates the mouse movement, and identify the mouse key click as well as the mouse roller rotation.
10. An operating method of a mouse chip, the mouse chip comprising a microcontroller, a bus arbiter, a first bus, a second bus, a cache controller, a flash controller and a flash memory, the operating method comprising:
generating, by the microcontroller, a function address of a function call;
performing, by the bus arbiter, address mapping on the function address to generate an operation address, and sending the operation address to the cache controller via the first bus;
caching, by the cache controller, a function return value generated by content at a corresponding flash address in the flash memory according to the operation address via the flash controller, and replying the function return value to the microcontroller via the first bus; and
stopping reading the function return value by the bus arbiter via the first bus when the microcontroller is sending update data to the bus arbiter, and sending, by the bus arbiter, the update data to the flash controller via the second bus to update first firmware in the flash memory.
11. The operating method as claimed in claim 10 , wherein the mouse chip further comprises a void hardware, and when the microcontroller is sending the update data to the bus arbiter, the operating method further comprises:
generating and replying, by the void hardware, a void return value conforming to a format of the function return value to the microcontroller to replace the function return value.
12. The operating method as claimed in claim 11 , wherein the void hardware is included in the bus arbiter or is an independent hardware outside the bus arbiter.
13. The operating method as claimed in claim 11 , wherein the microcontroller further comprises a register for recording the function address, and the operating method further comprises:
changing, by the void hardware, the function address in the register to a next program address.
14. The operating method as claimed in claim 10 , wherein the mouse chip further comprises at least one of a read only memory and a random access memory connected to the bus arbiter, and the read only memory or the random access memory is embedded with second firmware, and the operating method further comprises:
calculating a mouse movement and identifying a mouse key click as well as a mouse roller rotation by the second firmware when the first firmware is being updated.
15. A chip, comprising:
a flash memory, recorded with first firmware, and content of the flash memory being configured to operate a function called by the chip to generate a function return value, wherein
the chip is configured to
generate a function address of a function call,
cache the function return value in the flash memory into a cache memory,
read the function return value from the cache memory via a first bus, or update the first firmware in the flash memory via a second bus, and
generate a void return value conforming to a format of the function return value of the function to replace the function return value when updating the first firmware in the flash memory via the second bus.
16. The chip as claimed in claim 15 , wherein
the chip further comprises multiple registers configured to record the function address and a function return address of the function, and
the chip is further configured to change the function address and the function return address in the multiple registers when updating the first firmware in the flash memory via the second bus.
17. The chip as claimed in claim 15 , further comprising at least one of a read only memory and a random access memory, wherein the read only memory or the random access memory is embedded with second firmware.
18. The chip as claimed in claim 17 , wherein the second firmware is continuously operating when updating the first firmware in the flash memory via the second bus.