IP Library Granted Patent US 11,688,555
Granted Patent B2
US 11,688,555 · App. 17/137,498 · Granted Jun 27, 2023

Chip electronic component

Inventors: Yukihiro Fujita (Nagaokakyo, JP); Shogo Kanbe (Nagaokakyo, JP); Kosuke Nakano (Nagaokakyo, JP); Hideki Otsuka (Nagaokakyo, JP)
Assignee: MURATA MANUFACTURING CO., LTD.
H01G2/065H01G4/232H01G4/30H01G4/12H01G4/252
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Quick Facts
Patent No.
US 11,688,555
App. No.
17/137,498
Granted
Jun 27, 2023
Kind
B2
Abstract

A chip electronic component includes spacers that each have a predetermined thickness direction dimension on a mounting surface in a direction perpendicular to the mounting surface. The spacers each contain, as a main component, an intermetallic compound containing at least one high-melting-point metal selected from Cu and Ni, and Sn defining a low-melting-point metal.

Claims (34)

1. A chip electronic component comprising:

a chip component body including a mounting surface facing a mounting board;

at least two outer electrodes disposed on outer surfaces of the component body; and

at least two spacers respectively electrically connected to the at least two outer electrodes and at least partially disposed along the mounting surface of the component body;

wherein

each of the at least two spacers have a predetermined thickness direction dimension on the mounting surface in a direction perpendicular or substantially perpendicular to the mounting surface;

each of the at least two spacers contains an intermetallic compound containing at least one metal selected from Cu and Ni, and a simple Sn metal;

the chip component body has a rectangular or substantially rectangular parallelepiped shape including first and second main surfaces that oppose each other, first and second side surfaces that oppose each other, and first and second end surfaces that oppose each other, the first and second side surfaces and the first and second end surfaces connecting the first and second main surfaces, and the mounting surface is defined by the second main surface;

the at least two outer electrodes are respectively provided on the first and second end surfaces and respectively extend from the first and second end surfaces to portions of the first and second main surfaces and portions of the first and second side surfaces;

each of the at least two spacers is disposed on the second main surface and includes a portion in contact with a corresponding one of the at least two outer electrodes and a portion in contact with the second main surface; and

the at least two spacers are bonded to the mounting board by a bonding material.

2. The chip electronic component according to claim 1 , wherein the intermetallic compound is an intermetallic compound provided by a reaction between the Sn and a Cu—Ni alloy.

3. The chip electronic component according to claim 1 , wherein the chip electronic component is a multilayer ceramic capacitor.

4. The chip electronic component according to claim 3 , wherein the thickness direction dimension of each of the at least two spacers is about 10 μm or more.

5. The chip electronic component according to claim 1 , wherein each of the at least two spacers contains a simple Sn metal, in addition to the intermetallic compound.

6. The chip electronic component according to claim 1 , wherein outermost layers of at least portions of the at least two outer electrodes exposed from the at least two spacers are Sn-containing layers.

7. The chip electronic component according to claim 1 , wherein edges and corners of the component body are filleted.

8. The chip electronic component according to claim 1 , wherein the component body includes stacked ceramic layers and inner electrodes provided along interfaces between the ceramic layers.

9. The chip electronic component according to claim 8 , wherein the inner electrodes contain Ni as a conductive component.

10. The chip electronic component according to claim 8 , wherein each of the inner electrodes is connected to one of the at least two outer electrodes.

11. The chip electronic component according to claim 1 , wherein each of the at least two spacers further contains Ag.

12. The chip electronic component according to claim 1 , wherein an outermost layer of each of the at least two outer electrodes is an Sn plating layer.

13. The chip electronic component according to claim 1 , wherein the component body has a longitudinal direction dimension of about 1.12 mm, a width direction dimension of about 0.63 mm, and a height direction dimension of about 0.63 mm.

14. A chip electronic component comprising:

a chip component body including a mounting surface facing a mounting board;

at least two outer electrodes disposed on outer surfaces of the component body; and

at least two spacers respectively electrically connected to the at least two outer electrodes and at least partially disposed along the mounting surface of the component body;

wherein

each of the at least two spacers have a predetermined thickness direction dimension on the mounting surface in a direction perpendicular or substantially perpendicular to the mounting surface;

each of the at least two spacers contains at least one metal selected from Cu and Ni, and a simple Sn metal;

the chip component body has a rectangular or substantially rectangular parallelepiped shape including first and second main surfaces that oppose each other, first and second side surfaces that oppose each other, and first and second end surfaces that oppose each other, the first and second side surfaces and the first and second end surfaces connecting the first and second main surfaces, and the mounting surface is defined by the second main surface;

the at least two outer electrodes are respectively provided on the first and second end surfaces and respectively extend from the first and second end surfaces to portions of the first and second main surfaces and portions of the first and second side surfaces;

each of the at least two spacers is disposed on the second main surface and includes a portion in contact with a corresponding one of the at least two outer electrodes and a portion in contact with the second main surface; and

the at least two spacers are bonded to the mounting board by a bonding material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2020
From: FUJITA, YUKIHIRO; KANBE, SHOGO; NAKANO, KOSUKE; OTSUKA, HIDEKI
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 054774/0883 →
Priority Claims (1)
JP 2016-233717 · Dec 1, 2016 · national
Continuity (3)
Continuation 16427551 · May 31, 2019
Continuation PCTJP2017043063 · Nov 30, 2017
Related Publication 20210118614A1 · Apr 22, 2021
Cited By (1)
US 12,266,473