Switching circuits having drain connected ferrite beads
A circuit includes an electronic component package that comprises a first lead, a second lead, and a third lead; and a III-N transistor encased in the electronic component package, the III-N transistor including a drain, a gate, and a source, where the source is coupled to the first lead, the gate is coupled to the second lead, and the drain is coupled to the third lead. The circuit includes a high voltage node and a resistor, the resistor having a first terminal coupled to the high voltage node and a second terminal coupled to the third lead. The circuit further includes a ferrite bead connected in parallel to the resistor and coupled between the third lead and the high voltage node. When switching, the deleterious effects of a parasitic inductance of the circuit's power loop are mitigated by the ferrite bead and the resistor.
1. A circuit comprising:
a high side III-N transistor comprising:
a high side drain coupled to a high voltage node; and
a high side source coupled to a load node;
a low side III-N transistor comprising:
a low side drain coupled to the load node; and
a low side source coupled to a ground node;
a first ferrite bead coupled between the high side drain and the high voltage node and a second ferrite bead coupled between the low side source and the ground node; and
a resistor with a first terminal and a second terminal, wherein the first terminal of the resistor is coupled to the high side drain and the second terminal is coupled to the high-voltage node.
2. The circuit of claim 1 , further comprising a second resistor with a third terminal and a fourth terminal, wherein the third terminal is coupled to the low side source and the fourth terminal is coupled to the ground node.
3. The circuit of claim 1 , wherein the low side III-N transistor and/or the high side III-N transistor is a hybrid device comprising a depletion mode III-N transistor and an enhancement mode transistor.
4. The circuit of claim 1 , wherein the high side III-N transistor is implemented as two or more III-N transistors connected in parallel, and the low side III-N transistor is implemented as two or more III-N transistors connected in parallel.
5. The circuit of claim 4 , wherein each of the high side III-N transistors connected in parallel are coupled to their own respective additional ferrite beads between their high side drain and the high voltage node, and each of the low side III-N transistors connected in parallel are coupled to their own respective additional ferrite beads between their low side source and the ground node.
6. The circuit of claim 1 , wherein the high side III-N transistor is encased in an electronic component package, the electronic component package further comprising a conductive structural base, wherein the high side III-N transistor is a lateral III-N transistor, and the high side drain is electrically connected to the conductive structural base of the electronic component package.
7. The circuit of claim 1 , wherein the low side III-N transistor is encased in an electronic component package, the electronic component package further comprising a conductive structural base, wherein the low side III-N transistor is a lateral III-N transistor, and the low side source is electrically connected to the conductive structural base of the electronic component package.
8. The circuit of claim 1 , wherein the first ferrite bead and/or the second ferrite bead have an effective resistance between 100 and 500 at 100 MHz and a DC resistance of less than 10 mΩ.
9. The circuit of claim 1 , wherein a resistance of the resistor is less than an effective resistance of the ferrite bead at 100 MHz and greater than a DC resistance of the ferrite bead.
10. The circuit of claim 1 , wherein the first ferrite bead and/or the second ferrite bead are surface-mounted device (SMD) ferrite beads.