Miniaturized transistor structure with controlled dimensions of source/drain and contact-opening and related manufacture method

1. A manufacture method for a transistor which comprises a gate structure and a first conductive region, the manufacture method comprising:

forming an active region based on a substrate;

forming the gate structure and a dummy shield gate structure above the active region;

forming a first isolation region to replace the dummy shield gate structure;

forming a self-alignment pillar extending from a silicon surface of the substrate upward and above the active region; and

completely removing the self-alignment pillar and forming the first conductive region between the gate structure and the first isolation region, wherein the first conductive region is a source region or drain region.

2. The manufacture method in claim 1 , before the step of removing the self-alignment pillar, the manufacture method further comprising:

forming a second isolation region above the first isolation region, wherein the self-alignment pillar is between the gate structure and the second isolation region.

3. The manufacture method in claim 1 , after completely removing the self-alignment pillar, the manufacture method further comprising:

forming a spacer between the gate structure and the first isolation region to define a contact hole;

wherein the contact hole is above the first conductive region.

4. The manufacture method in claim 3 , wherein a length of the contact hole is less than a minimum feature length.

5. The manufacture method in claim 1 , wherein the substrate is a silicon substrate, and the self-alignment pillar is an intrinsic silicon pillar formed by selective epitaxy growth.

6. A manufacture method for a transistor which comprises a gate structure and a first conductive region, the manufacture method comprising:

forming an active region based on a substrate;

forming the gate structure based on the active region; and

forming a self-alignment pillar configured to allocate a contact hole above the first conductive region, wherein the first conductive region is formed after removing the self-alignment pillar, and the first conductive region is a source region or drain region.

7. The manufacture method in claim 6 , the manufacture method further comprising:

forming an isolation region based on the active region before forming the self-alignment pillar, wherein a selective epitaxy growth (SEG) technique is utilized to grow the self-alignment pillar.

8. The manufacture method in claim 7 , the manufacture method further comprising:

removing the self-alignment pillar which is formed between the gate structure and the isolation region; and

forming a spacer between the gate structure and the isolation region to define a contact hole; wherein the contact hole is above the first conductive region.

9. The manufacture method in claim 6 , wherein a length of the contact hole is less than a minimum feature length.

10. A manufacture method for a transistor which comprises a gate structure and a first conductive region, the manufacture method comprising:

forming an active region based on a substrate;

forming the gate structure above the active region;

forming the first conductive region next to the gate structure; and

defining a contact hole above the first conductive region, wherein defining the contact hole is independent from a photolithography process.

11. The manufacture method in claim 10 , wherein the first conductive region is formed between the gate structure and an isolation region which is extended upward above the active region.

12. The manufacture method in claim 11 , wherein the contact hole is defined by forming a spacer which covers a sidewall of the gate structure and a sidewall of the isolation region.

13. The manufacture method in claim 12 , wherein a length of the contact hole is less than a minimum feature length.

14. A manufacture method for a transistor which comprises a gate structure and a first conductive region, the manufacture method comprising:

implementing a first photolithography process configured to define a width of the gate structure and a length of an active region; and

implementing a second photolithography process which is configured to define a length of the gate structure in the active region;

wherein the second photolithography process is further configured to define a length of the first conductive region.

15. The manufacture method in claim 14 , wherein the length of the first conductive region defined by the second photolithography process is equal to or substantially equal to a minimum feature length.

16. The manufacture method in claim 14 , wherein a length of the gate structure defined by the second photolithography process is equal to or substantially equal to a minimum feature length.

17. The manufacture method in claim 14 , wherein a length of the active region defined by the first photolithography process is approximately equal to 4 times a minimum feature length.

18. A manufacture method for a transistor which comprises a gate structure and a first conductive region, the manufacture method comprising:

forming an active region based on a substrate;

forming the gate structure based on the active region;

forming the first conductive region next to the gate structure; and

forming a contact hole above the first conductive region without using a photolithography process to define a shape of the contact hole, wherein four sides of the contact hole are surrounded by a circumference of the first conductive region, and the contact hole extends upward from an original silicon surface of the substrate.

19. The manufacture method in claim 18 , wherein the first conductive region is formed between the gate structure and an isolation region.

20. The manufacture method in claim 19 , wherein the contact hole is defined by forming a spacer which covers a sidewall of the gate structure and a sidewall of the isolation region.

21. The manufacture method in claim 20 , wherein a length of the contact hole is less than a minimum feature length.