Display panel and display device using same

1. A display panel, comprising:

an active area including pixels arranged along a first direction and a second direction intersecting each other and data lines and gate lines arranged to be intersected; and

shift registers supplying a gate pulse to each of the gate lines,

wherein each of the shift registers includes:

GIP circuit portions dispersedly disposed in the active area; and

GIP lines supplying a predetermined signal to the GIP circuit portions or connecting the GIP circuit portions with each other, the GIP lines being located between neighboring pixels along the second direction,

wherein the active area includes a plurality of pixels arranged along the first direction and a plurality of pixel lines sequentially defined along the second direction; and

the GIP lines are located between a (2n−1)-th pixel line and a 2n-th pixel line, wherein n is a natural number greater than or equal to one, and

wherein the GIP lines include (2n−1)-th GIP lines and 2n-th GIP lines sequentially arranged along the second direction between the (2n−1)-th pixel line and the 2n-th pixel line that are neighboring along the second direction;

the (2n−1)-th GIP lines are connected to GIP circuit portions disposed in the (2n−1)-th pixel line;

the 2n-th GIP lines are connected to GIP circuit portions disposed in the 2n-th pixel line; and

the (2n−1)-th GIP lines and the 2n-th GIP lines are symmetrically arranged with respect to a virtual reference line extending in the first direction between the (2n−1)-th pixel line and the 2n-th pixel line that are neighboring.

2. The display panel of claim 1 , wherein the display panel includes:

a substrate;

TFTs disposed on the substrate;

an interlayer insulating film covering the TFTs;

a planarization film covering the interlayer insulating film;

an anode located on the planarization film and electrically connected to the corresponding TFT;

a bank layer having an opening exposing at least a part of the anode;

an organic compound layer located on the opening; and

a cathode located on the organic compound layer,

wherein at least one of the planarization layer and the bank layer is removed at one end and the other end in the second direction of the active area to form an open portion.

3. The display panel of claim 2 , wherein the GIP line is not located in the open portion.

4. The display panel of claim 1 , wherein the pixels include sub-pixels each including a light emitting element having an anode, a cathode, and an organic compound layer located between the anode and the cathode;

the active area includes an EVSS contact portion connecting the cathode and an EVSS line supplying a low potential pixel reference voltage to the cathode; and

the EVSS contact portion is selectively located between the 2n-th pixel line and the (2n+1)-th pixel line that are neighboring.

5. The display panel of claim 4 , wherein the EVSS contact portion includes:

at least one insulating layer interposed between the EVSS line and the cathode; and

an EVSS contact hole passing through the at least one insulating layer to connect the EVSS line and the cathode.

6. A display panel, comprising:

an active area including pixels arranged along a first direction and a second direction intersecting each other and data lines and gate lines arranged to be intersected; and

shift registers supplying a gate pulse to each of the gate lines,

wherein each of the shift registers includes:

GIP circuit portions dispersedly disposed in the active area; and

GIP lines supplying a predetermined signal to the GIP circuit portions or connecting the GIP circuit portions with each other, the GIP lines being located between neighboring pixels along the second direction,

wherein the active area includes a plurality of pixels arranged along the first direction and a plurality of pixel lines sequentially defined along the second direction; and

the GIP lines are located between a (2n−1)-th pixel line and a 2n-th pixel line, wherein n is a natural number greater than or equal to one, and

wherein the GIP lines include a 1-1 GIP line, a 1-2 GIP line, a 2-2 GIP line and a 2-1 GIP line sequentially arranged along the second direction between the (2n−1)-th pixel line and the 2n-th pixel line that are neighboring;

the 1-1 GIP line and the 1-2 GIP line are connected to GIP circuit portions disposed in the (2n−1)-th pixel line;

the 2-2 GIP line and the 2-1 GIP line are connected to GIP circuit portions disposed in the 2n-th pixel line;

a same type of signal is applied to the 1-1 GIP line and the 2-1 GIP line; and

a same type of signal is applied to the 1-2 GIP line and the 2-2 GIP line.

7. The display panel of claim 6 , wherein the signal applied to the 1-1 GIP line and the 2-1 GIP line is one of a clock and a power supply voltage; and

the signal applied to the 1-2 GIP line and the 2-2 GIP line is the other of the clock and the power supply voltage.

8. A display device, comprising:

a display panel including an active area including pixels arranged along a first direction and a second direction intersecting each other and data lines and gate lines arranged to be intersected;

a data driving circuit supplying data voltages to the data lines; and

a gate driving circuit sequentially supplying gate pulses to the gate lines,

wherein the gate driving circuit includes shift registers that supply a gate pulse to the gate lines; and

each of the shift registers includes:

GIP circuit portions dispersedly distributed in the active area; and

GIP lines supplying a predetermined signal to the GIP circuit portions or connecting the GIP circuit portions to each other, the GIP lines being selectively located only between neighboring pixels along the second direction,

wherein the active area includes a plurality of pixels arranged along the first direction and a plurality of pixel lines sequentially defined along the second direction; and

the GIP lines are located between a (2n−1)-th pixel line and a 2n-th pixel line, wherein n is a natural number greater than or equal to one, and

wherein the GIP lines include (2n−1)-th GIP lines and 2n-th GIP lines sequentially arranged along the second direction between the (2n−1)-th pixel line and the 2n-th pixel line that are neighboring along the second direction;

the (2n−1)-th GIP lines are connected to GIP circuit portions disposed in the (2n−1)-th pixel line;

the 2n-th GIP lines are connected to GIP circuit portions disposed in the 2n-th pixel line; and

the (2n−1)-th GIP lines and the 2n-th GIP lines are symmetrically arranged with respect to a virtual reference line extending in the first direction between the (2n−1)-th pixel line and the 2n-th pixel line that are neighboring.

9. A display device, comprising:

a display panel including an active area including pixels arranged along a first direction and a second direction intersecting each other and data lines and gate lines arranged to be intersected;

a data driving circuit supplying data voltages to the data lines; and

a gate driving circuit sequentially supplying gate pulses to the gate lines,

wherein the gate driving circuit includes shift registers that supply a gate pulse to the gate lines; and

each of the shift registers includes:

GIP circuit portions dispersedly distributed in the active area; and

GIP lines supplying a predetermined signal to the GIP circuit portions or connecting the GIP circuit portions to each other, the GIP lines being selectively located only between neighboring pixels along the second direction,

wherein the active area includes a plurality of pixels arranged along the first direction and a plurality of pixel lines sequentially defined along the second direction; and

the GIP lines are located between a (2n−1)-th pixel line and a 2n-th pixel line, wherein n is a natural number greater than or equal to one, and

wherein the GIP lines include a 1-1 GIP line, a 1-2 GIP line, a 2-2 GIP line and a 2-1 GIP line sequentially arranged along the second direction between the (2n−1)-th pixel line and the 2n-th pixel line that are neighboring;

the 1-1 GIP line and the 1-2 GIP line are connected to GIP circuit portions disposed in the (2n−1)-th pixel line;

the 2-2 GIP line and the 2-1 GIP line are connected to GIP circuit portions disposed in the 2n-th pixel line;

a same type of signal is applied to the 1-1 GIP line and the 2-1 GIP line; and

a same type of signal is applied to the 1-2 GIP line and the 2-2 GIP line.