Semiconductor package and method of fabricating the same

1. A semiconductor package, comprising:

a package substrate,

the package substrate including a cavity in the package substrate and a first vent hole,

the first vent hole extending from a top surface of the package substrate to the cavity such that first vent hole is in fluid communication with the cavity;

a first semiconductor chip mounted on the package substrate;

a second semiconductor chip mounted on a top surface of the first semiconductor chip; and

a first under-fill layer filling a space between the package substrate and the first semiconductor chip, the first under-fill layer extending along the first vent hole to fill the cavity, wherein

a width of the cavity is greater than a width of the first vent hole and less than a width of the first semiconductor chip.

2. The semiconductor package of claim 1 , further comprising:

a second under-fill layer filling a space between the first semiconductor chip and the second semiconductor chip, wherein

a width of the first under-fill layer between the package substrate and the first semiconductor chip is the same as or less than a width of the second under-fill layer between the first semiconductor chip and the second semiconductor chip.

3. The semiconductor package of claim 1 , wherein

the first vent hole is one of a plurality of first vent holes included in the package substrate, and

the plurality of first vent holes are arranged along a first direction and a second direction that are parallel to the top surface of the package substrate.

4. The semiconductor package of claim 1 , wherein a width of the first vent hole is in a range of about 2 μm to about 10 μm.

5. The semiconductor package of claim 1 , wherein

the package substrate includes a core portion, a first buildup portion, and a second buildup portion,

the core portion has a first surface and a second surface opposite to the first surface,

the first buildup portion and the second buildup portion are respectively on the first surface and the second surface,

each of the first buildup portion and the second buildup portions include a plurality of dielectric layers and a plurality of wiring lines that are alternately stacked, and

the cavity is in the core portion.

6. The semiconductor package of claim 1 , wherein

the package substrate includes a core portion, a first buildup portion, and a second buildup portion,

the core portion has a first surface and a second surface opposite to the first surface,

the first buildup portion and the second buildup portion are respectively on the first surface and the second surface,

each of the first buildup portion and the second buildup portion include a plurality of dielectric layers and a plurality of wiring lines that are alternately stacked, and

the cavity is in the second buildup portion.

7. The semiconductor package of claim 1 , wherein a distance between the package substrate and the first semiconductor chip is less than a distance between the first semiconductor chip and the second semiconductor chip.

8. The semiconductor package of claim 1 , wherein the package substrate further includes a second vent hole that extends from a bottom surface of the package substrate to the cavity and is in fluid communication with the cavity.

9. The semiconductor package of claim 8 , wherein the first under-fill layer extends from inside the cavity along the second vent hole onto the bottom surface of the package substrate.

10. The semiconductor package of claim 8 , wherein

the second vent hole is one of a plurality of second vent holes in the package substrate, and

the plurality of second vent holes are arranged along a first direction and a second direction that are parallel to the bottom surface of the package substrate.

11. The semiconductor package of claim 1 , wherein

the package substrate includes a plurality of substrate pads in a plurality of recessions on the top surface of the package substrate,

the plurality of substrate pads are exposed on the top surface of the package substrate,

the package substrate includes a plurality of connection terminals, and

the first semiconductor chip is coupled to the plurality of substrate pads through the plurality of connection terminals.

12. A semiconductor package, comprising:

a package substrate including a cavity therein;

a first semiconductor chip mounted through a first chip terminal on the package substrate;

a second semiconductor chip mounted through a second chip terminal on a top surface of the first semiconductor chip;

a first under-fill layer filling the cavity and a space between the package substrate and the first semiconductor chip;

a second under-fill layer filling a space between the first semiconductor chip and the second semiconductor chip, a width of the first under-fill layer between the package substrate and the first semiconductor chip being less than a width of the second under-fill layer between the first semiconductor chip and the second semiconductor chip; and

a molding layer on the package substrate, the molding layer surrounding the first semiconductor chip and the second semiconductor chip.

13. The semiconductor package of claim 12 , wherein

the package substrate further includes a first vent hole that extends from the cavity to a top surface of the package substrate, and

the first under-fill layer extends along the first vent hole to fill the cavity.

14. The semiconductor package of claim 12 , wherein

the package substrate further includes a second vent hole that extends from a bottom surface of the package substrate to the cavity and is fluid communication with the cavity, and

the first under-fill layer extends from inside the cavity along the second vent hole onto the bottom surface of the package substrate.

15. The semiconductor package of claim 12 , wherein

the package substrate includes a core portion, a first buildup portion on a top surface of the core portion, and a second buildup portion on a bottom surface of the core portion.

16. The semiconductor package of claim 15 , wherein the cavity is in the core portion of the package substrate.

17. The semiconductor package of claim 15 , wherein

the cavity is in the second buildup portion of the package substrate, and

the cavity is spaced apart from a wiring line of the second buildup portion.

18. A semiconductor package, comprising:

a package substrate including a cavity therein;

a first semiconductor chip mounted on the package substrate;

a second semiconductor chip mounted on a top surface of the first semiconductor chip;

a first under-fill layer filling a space between the package substrate and the first semiconductor chip, and extending into the cavity of the package substrate;

a second under-fill layer filling a space between the first semiconductor chip and the second semiconductor chip; and

a molding layer on the package substrate, the molding layer surrounding the first semiconductor chip and the second semiconductor chip,

wherein a protrusion distance of the second under-fill layer outwardly from a lateral surface of the second semiconductor chip is be greater than a protrusion distance of the first under-fill layer outwardly from a lateral surface of the first semiconductor chip.

19. The semiconductor package of claim 18 , wherein

the package substrate further includes a first vent hole that extends from the cavity to a top surface of the package substrate, and

the first under-fill layer extends along the first vent hole to fill the cavity.

20. The semiconductor package of claim 18 , wherein

a width of the first under-fill layer between the package substrate and the first semiconductor chip being less than a width of the second under-fill layer between the first semiconductor chip and the second semiconductor chip.