Method for manufacturing a membrane component and a membrane component

1. A method for manufacturing a membrane component with a membrane, the method comprising:

providing a semiconductor wafer ( 100 ) with a first layer ( 116 ), a second layer ( 118 ) and a third layer ( 126 );

depositing ( 12 ) a first masking layer ( 112 ) on the first layer ( 116 ), the first masking layer defining a first selectively processable area ( 114 ) for determining a geometry of the membrane (M 1 );

forming a first recess ( 120 ) by anisotropic etching of the first layer;

removing the first masking layer ( 112 );

introducing ( 14 ) a material ( 122 ) in the first recess ( 120 );

depositing ( 15 ) a membrane layer ( 124 ) on the first layer ( 116 ) with the introduced material ( 122 );

depositing on the third layer ( 126 ) a second masking layer that defines a second selectively processable area;

forming a second recess by anisotropic etching of the third layer ( 126 ) and of the second layer ( 118 ) up to the first layer ( 116 );

removing the second masking layer;

after the removal of the second masking layer, depositing ( 16 ) a fourth layer ( 152 ) on the third layer ( 126 ), on the first layer ( 116 ) and on at least one sidewall of the second recess created by anisotropically etching the third ( 126 ) and the second layer ( 118 ); and

anisotropically etching ( 17 ) an area of the fourth layer ( 152 ), the area of the fourth layer ( 152 ) contacting the first layer ( 116 ), up to the first layer; and

isotropically etching ( 18 ) the first layer ( 116 ), the isotropic etching being limited by the membrane layer ( 124 ) and by the introduced material ( 122 ), so that the membrane (M 1 ) will be exposed.

2. The method according to claim 1 , wherein the first layer ( 116 ) comprises a material different from that of the second layer ( 118 ).

3. The method according to claim 1 , wherein the first layer ( 116 ) comprises a silicon layer and the second layer ( 118 ) comprises an oxide layer.

4. The method according to claim 1 , wherein the semiconductor wafer ( 100 ) is a silicon-on-insulator wafer.

5. The method according to claim 1 , wherein the first layer ( 116 ) has a first layer thickness (d 1 ) smaller than a fourth thickness (d 4 ) resulting from the summation of a second layer thickness (d 2 ) of the second layer ( 118 ) and a third layer thickness (d 3 ) of the third layer ( 126 ).

6. The method according to claim 5 , wherein a ratio of the first layer thickness (d 1 ) to the fourth thickness (d 4 ) lies between 1:10 and 1:200.

7. The method according to claim 6 , wherein a ratio of the first layer thickness (d 1 ) to the fourth thickness (d 4 ) lies between 1:50 and 1:150.

8. The method according to claim 7 , wherein a ratio of the first layer thickness (d 1 ) to the fourth thickness (d 4 ) lies between 1:50 and 1:100.

9. The method according to claim 1 , wherein a fourth layer ( 152 ) comprises a passivation layer.

10. The method according to claim 1 , wherein at least the first or at least the second masking layer comprises a photoresist.

11. The method according to claim 1 , wherein the first and the second masking layer are produced by means of photolithography.

12. The method according to claim 1 , wherein the membrane (M 1 ) has a circular, a rectangular, a polygonal, or a non-circular basic shape.

13. The method according to claim 1 , wherein the membrane (M 1 ) has at least one opening ( 150 ).

14. The method according to claim 13 , wherein the membrane (M 1 ) is perforated.

15. A method for manufacturing a membrane component with a membrane, the method comprising:

providing a semiconductor wafer ( 100 ) with a first layer ( 116 ), a second layer ( 118 ) and a third layer ( 126 );

depositing ( 12 ) a first masking layer ( 112 ) on the first layer ( 116 ), the first masking layer defining a first selectively processable area ( 114 ) for determining a geometry of the membrane (M 1 );

forming a first recess ( 120 ) by anisotropic etching of the first layer;

removing the first masking layer ( 112 );

introducing ( 14 ) a material ( 122 ) in the first recess ( 120 );

depositing ( 15 ) a membrane layer ( 124 ) on the first layer ( 116 ) with the introduced material ( 122 );

depositing on the third layer ( 126 ) a second masking layer that defines a second selectively processable area;

forming a second recess by anisotropic etching of the third layer ( 126 ) and of the second layer ( 118 ) up to the first layer ( 116 );

removing the second masking layer;

polishing the first layer ( 116 ) with the introduced material ( 122 ) prior to applying ( 15 ) the membrane layer ( 124 ); and

isotropically etching ( 18 ) the first layer ( 116 ), the isotropic etching being limited by the membrane layer ( 124 ) and by the introduced material ( 122 ), so that the membrane (M 1 ) will be exposed.

16. The method according to claim 15 , wherein the polishing is a chemical-mechanical polishing.

17. A method for manufacturing a membrane component with a membrane, the method comprising:

providing a semiconductor wafer ( 100 ) with a first layer ( 116 ), a second layer ( 118 ) and a third layer ( 126 );

depositing ( 12 ) a first masking layer ( 112 ) on the first layer ( 116 ), the first masking layer defining a first selectively processable area ( 114 ) for determining a geometry of the membrane (M 1 );

forming a first recess ( 120 ) by anisotropic etching of the first layer;

removing the first masking layer ( 112 );

introducing ( 14 ) a material ( 122 ) in the first recess ( 120 ) wherein the introduced material ( 122 ) and the second layer ( 118 ) comprise an identical material;

depositing ( 15 ) a membrane layer ( 124 ) on the first layer ( 116 ) with the introduced material ( 122 );

depositing on the third layer ( 126 ) a second masking layer that defines a second selectively processable area;

forming a second recess by anisotropic etching of the third layer ( 126 ) and of the second layer ( 118 ) up to the first layer ( 116 );

removing the second masking layer; and

isotropically etching ( 18 ) the first layer ( 116 ), the isotropic etching being limited by the membrane layer ( 124 ) and by the introduced material ( 122 ), so that the membrane (M 1 ) will be exposed.

18. A method for manufacturing a membrane component with a membrane, the method comprising:

providing a semiconductor wafer ( 100 ) with a first layer ( 116 ), a second layer ( 118 ) and a third layer ( 126 );

depositing ( 12 ) a first masking layer ( 112 ) on the first layer ( 116 ), the first masking layer defining a first selectively processable area ( 114 ) for determining a geometry of the membrane (M 1 ) wherein the membrane (M 1 ) has at least one opening ( 150 );

forming a first recess ( 120 ) by anisotropic etching of the first layer;

removing the first masking layer ( 112 );

introducing ( 14 ) a material ( 122 ) in the first recess ( 120 );

depositing ( 15 ) a membrane layer ( 124 ) on the first layer ( 116 ) with the introduced material ( 122 );

depositing on the third layer ( 126 ) a second masking layer that defines a second selectively processable area;

forming a second recess by anisotropic etching of the third layer ( 126 ) and of the second layer ( 118 ) up to the first layer ( 116 );

removing the second masking layer; and

isotropically etching ( 18 ) the first layer ( 116 ), the isotropic etching being limited by the membrane layer ( 124 ) and by the introduced material ( 122 ), so that the membrane (M 1 ) will be exposed, wherein the isotropic etching is carried out through the at least one opening ( 150 ) of the membrane (M 1 ).