Semiconductor device including three-dimensional field-effect transistor with curved multi-layered source/drain pattern
A semiconductor device including an active pattern extending in a first direction; a channel pattern on the active pattern and including vertically stacked semiconductor patterns; a source/drain pattern in a recess in the active pattern; a gate electrode on the active pattern and extending in a second direction crossing the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns; and a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns, wherein the source/drain pattern includes a buffer layer covering inner sides of the recess, the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, and each of the outer and inner side surfaces is a curved surface that is convexly curved toward a closest gate electrode.
1. A semiconductor device, comprising
a first active pattern on a first active region of a substrate, the first active pattern extending in a first direction;
a first channel pattern on the first active pattern, the first channel pattern including semiconductor patterns, which are vertically stacked;
a first source/drain pattern in a recess in an upper portion of the first active pattern;
a gate electrode on the first active pattern and extending in a second direction crossing the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns; and
a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns,
wherein:
the first source/drain pattern includes a buffer layer covering inner sides of the recess,
when viewed in a plan view, the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, and
when viewed in a plan view, each of the outer and inner side surfaces is a curved surface that is convexly curved toward the gate electrode closest to the buffer layer.
2. The semiconductor device as claimed in claim 1 , wherein:
the gate spacer includes a first spacer sidewall, which faces the first direction, and a second spacer sidewall, which is an inner sidewall of the opening, and
the buffer layer fully covers the second spacer sidewall, when viewed in a plan view.
3. The semiconductor device as claimed in claim 2 , wherein:
the first source/drain pattern further includes a main layer on the buffer layer to fill the recess, and
the main layer covers at least a portion of the first spacer sidewall of the gate spacer and is spaced apart from the second spacer sidewall.
4. The semiconductor device as claimed in claim 2 , wherein the inner side surface of the buffer layer is continuous with the first spacer sidewall of the gate spacer.
5. The semiconductor device as claimed in claim 2 , wherein:
the first source/drain pattern further includes an intermediate layer on the inner side surface of the buffer layer, when viewed in a plan view,
the second spacer sidewall includes a first surface and a second surface, which face the opening and are opposite to each other,
the buffer layer fills the opening and covers the first surface and the second surface, and
the first surface and the second surface are spaced apart from the intermediate layer.
6. The semiconductor device as claimed in claim 1 , wherein:
the buffer layer fills the opening,
the buffer layer has a sidewall center thickness at a center of the opening and a sidewall edge thickness at an edge of the opening, when viewed in a plan view, and
the sidewall center thickness is equal to the sidewall edge thickness.
7. The semiconductor device as claimed in claim 1 , wherein:
the recess has a pair of inner side surfaces and a bottom surface connecting the inner side surfaces,
the buffer layer includes a pair of side portions on the pair of inner side surfaces, and a center portion connected to the pair of side portions and on the bottom surface of the recess,
when viewed in a plan view, the side portions are spaced apart from each other by a first distance in the first direction, at a center portion of the opening,
the side portions are spaced apart from each other by a second distance in the first direction, at an edge portion of the opening adjacent to the gate spacer, and
the first distance is larger than the second distance.
8. The semiconductor device as claimed in claim 1 , wherein:
the first source/drain pattern further includes a main layer on the buffer layer to fill the recess, and
a concentration of germanium (Ge) in the main layer ranges from 60 at % to 80 at %.
9. The semiconductor device as claimed in claim 1 , wherein:
the recess has a pair of inner side surfaces and a bottom surface connecting the inner side surfaces,
the buffer layer covers the pair of inner side surfaces of the recess and exposes the bottom surface of the recess, and
the inner side surface of the buffer layer is vertically aligned to a side surface of the gate spacer.
10. The semiconductor device as claimed in claim 1 , wherein:
the recess includes a pair of inner side surfaces and a bottom surface connecting the inner side surfaces,
the buffer layer includes side portions on the pair of inner side surfaces of the recess, a center portion on the bottom surface of the recess, and an edge portion connecting the side portions to the center portion, and
a thickness of the edge portion is smaller than a maximum thickness of each of the side portions.
11. The semiconductor device as claimed in claim 1 , wherein:
the recess includes a pair of inner side surfaces and a bottom surface connecting the inner side surfaces,
the buffer layer includes side portions on the pair of inner side surfaces of the recess and a center portion on the bottom surface of the recess,
each of the side portions has a first thickness at a first level and has a second thickness at a second level lower than the first level,
the side portions has a maximum width in the first direction, at the first level, and
the first thickness is larger than the second thickness.
12. A semiconductor device, comprising
a first active pattern on a first active region of a substrate, the first active pattern extending in a first direction;
a first channel pattern on the first active pattern, the first channel pattern including semiconductor patterns, which are vertically stacked;
a first source/drain pattern in a recess of an upper portion of the first active pattern;
a gate electrode on the first active pattern and extending in a second direction crossing the first direction; and
a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns,
wherein:
the first source/drain pattern includes a buffer layer covering inner sides of the recess, a main layer on the buffer layer to fill the recess, and an intermediate layer between the buffer layer and the main layer,
the gate spacer includes a first spacer sidewall facing in the first direction, and a second spacer sidewall, which is an inner sidewall of the opening, when viewed in a plan view,
the buffer layer covers the second spacer sidewall, and
the second spacer sidewall is spaced apart from the main layer.
13. The semiconductor device as claimed in claim 12 , wherein:
the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, when viewed in a plan view, and
the inner side surface is continuous with the first spacer sidewall.
14. The semiconductor device as claimed in claim 13 , wherein each of the outer side surface and the inner side surface is a curved surface that is convexly curved toward the gate electrode closest to the buffer layer.
15. The semiconductor device as claimed in claim 12 , wherein:
the buffer layer fills the opening,
the buffer layer has a sidewall center thickness at a center of the opening and a sidewall edge thickness at an edge of the opening, when viewed in a plan view, and
the sidewall center thickness is equal to the sidewall edge thickness.
16. The semiconductor device as claimed in claim 12 , wherein:
the recess has a pair of inner side surfaces and a bottom surface connecting the inner side surfaces,
the buffer layer has a pair of side portions on the pair of inner side surfaces, and a center portion connected to the pair of side portions and on the bottom surface,
when viewed in a plan view, the side portions are spaced apart from each other by a first distance in the first direction, at a center portion of the opening,
the side portions are spaced apart from each other by a second distance in the first direction, at an edge portion of the opening adjacent to the gate spacer, and
the first distance is larger than the second distance.
17. The semiconductor device as claimed in claim 12 , wherein:
the recess has a pair of inner side surfaces and a bottom surface connecting the inner side surfaces,
the buffer layer covers the pair of inner side surfaces of the recess and exposes the bottom surface of the recess, and
the inner side surface of the buffer layer is vertically aligned to a side surface of the gate spacer.
18. The semiconductor device as claimed in claim 12 , wherein:
the recess includes a pair of inner side surfaces and a bottom surface connecting the inner side surfaces,
the buffer layer includes side portions on the pair of inner side surfaces of the recess and a center portion on the bottom surface of the recess,
each of the side portions has a first thickness at a first level and has a second thickness at a second level lower than the first level,
the side portions have a maximum width in the first direction, at the first level, and
the first thickness is larger than the second thickness.
19. A semiconductor device, comprising
a substrate including a first active region and a second active region;
a first active pattern on the first active region of the substrate and extending in a first direction;
a first source/drain pattern in a first recess of an upper portion of the first active pattern;
a second active pattern on the second active region of the substrate and extending in the first direction;
a second source/drain pattern in a second recess of an upper portion of the second active pattern;
a gate electrode on a first channel pattern of the upper portion of the first active pattern and a second channel pattern of the upper portion of the second active pattern and extending in a second direction crossing the first direction, each of the first and second channel patterns including semiconductor patterns, which are vertically stacked, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns,
a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns;
active contacts connected to the first source/drain pattern and the second source/drain pattern;
a plurality of interconnection lines connected to the active contacts;
a plurality of vias provided below the interconnection lines; and
interlayer insulating layers covering the active contacts, the interconnection lines, and the vias,
wherein:
the first source/drain pattern includes a buffer layer covering inner sides of the first recess, an intermediate layer on the buffer layer, and a main layer on the intermediate layer to fill a remaining space of the first recess,
when viewed in a plan view, the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, and
the outer side surface and the inner side surface are curved surfaces that are convexly curved toward the gate electrode closest to the buffer layer.
20. The semiconductor device as claimed in claim 19 , wherein:
the buffer layer fills the opening,
the buffer layer has a sidewall center thickness at a center of the opening and has a sidewall edge thickness at an edge of the opening, when viewed in a plan view, and
the sidewall center thickness is equal to the sidewall edge thickness.