MRAM architecture with multiplexed sense amplifiers and direct write through buffers
View Patent ↗A magnetic memory device for storing and quickly retrieving data from an array of magnetic memory elements. The array includes a plurality of magnetic memory element such as magnetic tunnel junction elements arranged in rows and columns. A plurality of multiplexed bit lines is connected with a first end of each of the magnetic memory elements and plurality of multiplexed source lines are connected with a second end of each of the magnetic memory elements. The multiplexing allows source line current and/or bit line current to be applied to an individual column of memory elements in the array for quick retrieval of data in a Magnetic Random Access Memory (MRAM) system.
1. A magnetic memory device, comprising:
an array of magnetic memory elements arranged in rows and columns;
a plurality of multiplexed bit-line selector transistors that each connects with a respective bit line of a respective column of magnetic memory elements, the multiplexing allowing for a selection of an individual column of magnetic memory elements within the array by selecting a respective bit-line selector transistor connected to a corresponding column of magnetic memory elements in the array, wherein the plurality of multiplexed bit-line selector transistors selectively connect a bit line to a bit-line write circuit, and the bit-line write circuit provides a write current to the bit line selected by the respective bit-line selector transistor, the write current being applied to the bit line of the corresponding column of magnetic memory elements to switch a memory state of the corresponding column of magnetic memory elements; and
a plurality of multiplexed source-line selector transistors that are different from the bit-line selector transistors and each source-line selector transistor connects with a respective source line of a respective column of magnetic memory elements, the multiplexing allowing selection of an individual column in the array by selecting a respective source-line selector transistor connected to a corresponding column of magnetic memory elements in the array, wherein the plurality of multiplexed source-line selector transistors selectively connect a source line to a source-line read/write circuit, and the source-line read/write circuit to apply a read current or a write current to the source line selected by the respective source-line selector transistor.
2. The magnetic memory device as in claim 1 , further comprising a word line connected with the array for selecting a row of memory elements.
3. The magnetic memory device as in claim 1 , wherein each of the magnetic memory elements is connected with an associated bit-line selector transistor and an associated source-line selector transistor.
4. The magnetic memory device as in claim 3 , further comprising a word line configured to apply a gate voltage to at least one of the selector transistors.
5. The magnetic memory device as in claim 1 , wherein each of the plurality of magnetic memory devices is a magnetic tunnel junction element.
6. The magnetic memory device as in claim 1 , wherein each of the plurality of magnetic memory devices is a perpendicular magnetic tunnel junction element.