Processing-in-memory (PIM) device

1. A processing-in-memory (PIM) device comprising:

a data storage region configured to store first data and second data; and

a multiplication/accumulation (MAC) operator configured to perform a MAC arithmetic operation of the first data and the second data,

wherein the MAC operator includes:

a MAC circuit configured to perform the MAC arithmetic operation to output MAC result data; and

a data output unit configured to feedback bias data to the MAC circuit prior to the MAC arithmetic operation, and

wherein the data output unit includes:

a data selector configured to receive the bias data and the MAC result data and configured to selectively output the bias data or the MAC result data based on a selection signal; and

a data output latch configured to receive output data of the data selector to feedback the output data of the data selector to the MAC circuit;

a delay circuit configured to receive and delay the selection signal by a certain time to output a delayed selection signal; and

an OR gate configured to perform a logical OR operation of an output signal of the delay circuit and a clock signal of the data output latch to output a result of the logical OR operation to a clock terminal of the data output latch.

2. The PIM device of claim 1 , wherein the MAC operator further includes a data input unit configured to:

receive the first data and the second data from the data storage region; and

latch the first data and the second data.

3. The PIM device of claim 2 , wherein the MAC circuit includes:

an arithmetic block configured to perform the MAC arithmetic operation of the first and second data to output MAC interim data; and

an accumulative addition logic circuit configured to perform a bias addition operation for adding feedback data, which are outputted from the data output unit, to the MAC interim data outputted from the arithmetic block to generate and output the MAC result data.

4. The PIM device of claim 1 , wherein the data output latch is configured to set the bias data as initial feedback data.

5. The PIM device of claim 4 , wherein the data output unit is configured to latch the MAC result data when the data output unit receives the MAC result data from the data selector.

6. The PIM device of claim 1 ,

wherein the MAC circuit includes:

an arithmetic block configured to perform the MAC arithmetic operation of the first and second data to output MAC interim data; and

an accumulative addition logic circuit configured to perform a bias addition operation for adding feedback data, which are outputted from the data output unit, to the MAC interim data outputted from the arithmetic block to generate and output the MAC result data,

wherein the PIM device further comprises a control signal generator configured to output first, second, third, and fourth control signals for controlling operations of the MAC operator,

wherein the first control signal is the selection signal, which is inputted to the data selector, for selectively outputting one of the bias data and the MAC result data from the data selector,

wherein the second control signal is a control signal, which is inputted to the data input unit, for transmitting the first data from the data input unit to the arithmetic block,

wherein the third control signal is a control signal, which is inputted to the data input unit, for transmitting the second data from the data input unit to the arithmetic block, and

wherein the fourth control signal is the clock signal of the data output latch for outputting output data of the accumulative addition logic circuit from the data output latch.

7. The PIM device of claim 6 , wherein the control signal generator is configured to:

output the first control signal having a logic “high” level at a first point in time;

output the second control signal at a second point in time when a first latency elapses from the first point in time;

output the third control signal at a third point in time when a second latency elapses from the second point in time;

output the fourth control signal at a fourth point in time when a third latency elapses from the third point in time; and

change a logic level of the first control signal from a logic “high” level into a logic “low” level at the second point in time.

8. The PIM device of claim 1 ,

wherein the data selector is configured to output the bias data to the data output latch when the first control signal has a first logic level; and

wherein the data output latch is synchronized with an output signal of the OR gate to output the bias data received from the data selector.

9. The PIM device of claim 1 , wherein the data selector is configured to output the MAC result data to the data output latch when the first control signal has a second logic level.

10. A processing-in-memory (PIM) device comprising:

a multiplication/accumulation (MAC) circuit including an arithmetic block and an accumulative addition logic circuit, wherein the arithmetic block is configured to perform a MAC arithmetic operation of first data and second data to output MAC interim data and the accumulative addition logic circuit is configured to add feedback data to the MAC interim data to output MAC result data;

a data output unit configured to set the MAC result data as the feedback data to transmit the feedback data to the accumulative addition logic circuit; and

an input control circuit configured to supply the first and second data to the MAC circuit,

wherein the input control circuit is configured to supply first preliminary data and second preliminary data to the MAC circuit before the first and second data are supplied to the MAC circuit,

wherein bias data are outputted as the MAC result data by the MAC arithmetic operation of the first and second preliminary data, and

wherein the input control circuit includes:

a first data selector configured to receive the first data and the first preliminary data and configured to selectively output the first data or the first preliminary data according to a selection signal; and

a second data selector configured to receive the second data and the second preliminary data and configured to selectively output the second data or the second preliminary data according to the selection signal.

11. The PIM device of claim 10 , further comprising a data input unit configured to receive and latch output data of the input control circuit.

12. The PIM device of claim 11 , wherein the data output unit includes a data output latch which is configured to receive the MAC result data from the MAC circuit to output the MAC result data as the feedback data.

13. The PIM device of claim 12 , wherein the data output latch is configured to set the bias data as initial data of the feedback data.

14. The PIM device of claim 12 , further comprising a control signal generator configured to output first, second, third, and fourth control signals for controlling operations of the input control circuit, the MAC circuit, the data input unit, and the data output unit,

wherein the first control signal is a control signal corresponding to the selection signal, which is inputted to the input control circuit, for selectively outputting both of the first and second data or both of the first and second preliminary data from the input control circuit;

wherein the second control signal is a control signal, which is inputted to the data output latch, for outputting input data of the data output latch from the data output latch;

wherein the third control signal is a control signal, which is inputted to the input control circuit, for transmitting the first data from the data input unit to the arithmetic block; and

wherein the fourth control signal is a control signal, which is inputted to the input control circuit, for transmitting the second data from the data input unit to the arithmetic block.

15. The PIM device of claim 14 , wherein the input control circuit further includes:

a delay circuit configured to receive and delay the first control signal by a certain time to output the delayed first control signal;

a first OR gate configured to perform a logical OR operation of an output signal of the delay circuit and the third control signal to output a result of the logical OR operation to the data input unit; and

a second OR gate configured to perform a logical OR operation of the output signal of the delay circuit and the fourth control signal to output a result of the logical OR operation to the data input unit.

16. The PIM device of claim 15 , wherein the control signal generator is configured to:

output the first control signal having a first logic level at a first point in time;

output the second control signal at a second point in time when a first latency elapses from the first point in time;

output the third control signal at a third point in time when a second latency elapses from the second point in time;

output the fourth control signal at a fourth point in time when a third latency elapses from the third point in time; and

change a logic level of the first control signal from the first logic level into a second logic level at the second point in time.

17. The PIM device of claim 14 ,

wherein the first data selector is configured to output the first preliminary data when the first control signal having a first logic level is set as the selection signal and output the first data when the first control signal having a second logic level is set as the selection signal; and

wherein the second data selector is configured to output the second preliminary data when the first control signal having the first logic level is set as the selection signal and output the second data when the first control signal having the second logic level is set as the selection signal.

18. The PIM device of claim 14 , wherein the data output latch is configured to be synchronized with the second control signal to output the MAC result data received from the MAC circuit.