Semiconductor device having vertical DMOS and manufacturing method thereof

1. A semiconductor device comprising:

a substrate;

a buried doped layer formed on the substrate;

a trench gate formed on the buried doped layer;

a source region formed adjacent the trench gate;

an interlayer dielectric layer formed on the trench gate and the source region;

a source contact plug formed to extend and connect to the source region; and

a drain contact plug, extending and connecting to the buried doped layer, formed deeper than the source contact plug,

wherein the trench gate includes a plurality of trench gates surrounding the drain contact plug.

2. The device of claim 1 , wherein a bottom surface of the drain contact plug is located deeper than a bottom surface of the trench gate.

3. The device of claim 1 , wherein the drain contact plug is formed to extend from the interlayer dielectric layer to the buried doped layer.

4. The device of claim 1 , wherein a width of the drain contact plug is greater than a width of the trench gate.

5. The device of claim 1 , wherein a width of the drain contact plug is greater than a width of the source contact plug.

6. The device of claim 1 , further comprising:

a drift region formed on the buried doped layer;

a body region formed in the drift region;

a body contact region formed in the body region;

a source metal wiring connected to the source contact plug; and

a drain metal wiring connected to the drain contact plug,

wherein the drain contact plug is formed to extend through the body region and the drift region to the buried doped layer.

7. The device of claim 1 , wherein the drain contact plug is formed in a drain contact hole.

8. The device of claim 1 , further comprising a middle trench filled with a gap-fill dielectric material to surround the drain contact plug and to be in direct contact with the buried doped layer.

9. The device of claim 8 , further comprising:

a shallow trench having a depth shallower than a depth of the middle trench; and

a deep trench having a depth deeper than the depth of the middle trench,

wherein the shallow trench is filled with the gap-fill dielectric material, and the deep trench is filled with the interlayer dielectric layer.

10. The device of claim 9 , wherein the deep trench is formed to be deeper than the buried doped layer, and an air gap is formed in the deep trench.

11. The device of claim 1 , wherein the buried doped layer is a drain region, and

wherein the semiconductor device is a vertical Double-Diffused Metal-Oxide-Semiconductor (DMOS) device, and an electron movement path is formed in a direction perpendicular to a surface of the substrate.

12. The device of claim 1 , wherein the source contact plug includes a plurality of source contact plugs, and the plurality of source contact plugs surround the drain contact plug, and the drain contact plug is located at a center of the plurality of source contact plugs.

13. The device of claim 1 , further comprising a Complementary Metal-Oxide-Semiconductor (CMOS) device, an extended drain MOS (EDMOS) device, and a bipolar junction transistor (BJT) device on the substrate.

14. A method of manufacturing a semiconductor device, the method comprising:

forming a trench gate formed in a substrate;

forming a source region adjacent the trench gate;

forming an interlayer dielectric layer on the trench gate and the source region;

forming a drain contact plug by etching the interlayer dielectric layer and the substrate; and

forming a source contact plug extended to connect to the source region by etching the interlayer dielectric layer;

forming a shallow trench in the substrate; and

forming a deep trench in the substrate,

wherein a depth of a bottom surface of the drain contact plug is deeper than a bottom surface of the shallow trench and shallower than a bottom surface of the deep trench, and

wherein the drain contact plug is formed to be deeper than the source contact plug.

15. The method of claim 14 , further comprising:

forming a middle trench in the substrate; and

forming a gap-fill dielectric material in the middle trench,

wherein the drain contact plug is formed in the gap-fill dielectric material.

16. The method of claim 15 , wherein the forming of the drain contact plug comprises:

forming a drain contact mask pattern on the interlayer dielectric layer;

etching the interlayer dielectric layer using the drain contact mask pattern;

forming a drain contact hole by etching the gap-fill dielectric material in the middle trench; and

filling the drain contact hole with a conductive material.

17. The method of claim 14 , further comprising forming a buried doped layer on the substrate,

wherein the drain contact plug is formed to extend from the interlayer dielectric layer to the buried doped layer.

18. The method of claim 17 , further comprising:

forming a drift region on the buried doped layer;

forming a body region in the drift region;

forming a body contact region in the body region; and

forming a source metal wiring connected to the source contact plug and a drain metal wiring connected to the drain contact plug.

19. The method of claim 18 , wherein the drain contact plug extends through the body region and the drift region to the buried doped layer.

20. The method of claim 14 , wherein the deep trench is filled with the interlayer dielectric layer, and an air gap is formed in the deep trench.

21. The method of claim 14 , further comprising forming a Complementary Metal-Oxide-Semiconductor (CMOS) device, an extended drain MOS (EDMOS) device, and a bipolar junction transistor (BJT) device on the substrate.

22. A semiconductor device comprising:

a buried doped layer formed on a substrate;

a drift region and a trench gate formed on the buried doped layer;

a body region formed in the drift region; and

a drain contact plug formed in the body region, the drift region, and the buried doped layer,

wherein the trench gate includes a plurality of trench gates surrounding the drain contact plug.

23. The device of claim 22 , further comprising:

a source region and a body contact region formed in the body region;

an interlayer dielectric layer formed on the trench gate; and

a source contact plug connected to the source region,

wherein a length of the drain contact plug is longer than a length of the source contact plug.

24. The device of claim 23 , further comprising:

a source metal wiring formed on the interlayer dielectric layer and connected to the source contact plug; and

a drain metal wiring formed on the interlayer dielectric layer and connected to the drain contact plug.

25. The device of claim 23 , wherein the drain contact plug is formed from the interlayer dielectric layer to the buried doped layer.

26. A semiconductor device comprising:

a buried doped layer formed between a substrate and an interlayer dielectric layer;

source contact plugs each formed to extend and connect to a source region;

a drain contact plug formed, deeper than the source contact plugs, between adjacent ones to the source contact plugs to extend and connect to the buried doped layer; and

trench gates each opposingly formed about the drain contact plug,

wherein one of the trench gates is formed between the drain contact plug and one of the source contact plugs and another of the trench gates is formed between the drain contact plug and another of the source contact plugs.

27. The device of claim 26 , wherein the source region is formed adjacent the one of the trench gates.

28. The device of claim 27 , further comprising:

a drift region formed on the buried doped layer;

a body region formed in the drift region; and

a body contact region formed in the body region,

wherein the drain contact plug is formed to extend to the buried doped layer through the body region and the drift region.