IP Library › Granted Patent US 11,751,446
Granted Patent B2
US 11,751,446 · App. 17/150,595 · Granted Sep 5, 2023

Display device having first, second, third and fourth transistors, and electronic apparatus

Inventors: Takumi Kodama (Suwa, JP); Takeshi Koshihara (Matsumoto, JP)
Assignee: SEIKO EPSON CORPORATION
H10K59/131H10K59/1213
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Quick Facts
Patent No.
US 11,751,446
App. No.
17/150,595
Granted
Sep 5, 2023
Kind
B2
Abstract

The display device includes a pixel circuit provided corresponding to a data line and a scanning line, the pixel circuit includes first to fourth transistors and a display element, and the first transistor supplies a current in accordance with a voltage between a gate node and a source node to the display element via the fourth transistor, the second transistor is disposed between the data line and the gate node of the first transistor and is turned on and off in accordance with a potential of the scanning line, the third transistor is disposed between the data line and a drain node of the first transistor, and the fourth transistor is disposed between the drain node of the first transistor and the display element.

Claims (44)

1. A display device comprising:

a pixel circuit provided corresponding to a data line and a scanning line, wherein

the pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a display element,

the first transistor supplies a current in accordance with a voltage between a gate node of the first transistor and a source node of the first transistor to the display element via the fourth transistor,

the second transistor is disposed between the data line and the gate node of the first transistor and is turned on or off in accordance with a potential of the scanning line,

the third transistor is disposed between the data line and a drain node of the first transistor,

the fourth transistor is disposed between the drain node of the first transistor and the display element, wherein

in a first period, the second transistor is on state, the third transistor and the fourth transistor are off state, and a voltage that turns on the first transistor is applied to the gate node of the first transistor via the data line,

in a second period after the first period, the second transistor and the third transistor are on state, and the fourth transistor is off state, and

in a third period after the second period, the second transistor is on state, the third transistor and the fourth transistor are off state, and a data signal having a voltage in accordance with a current flowing to the display element is supplied to the data line.

2. The display device according to claim 1 , wherein

in a fourth period after the third period, the fourth transistor is on state, and a current flows to the display element via the first transistor and the fourth transistor.

3. The display device according to claim 2 , wherein

the fourth transistor includes a gate node,

in the fourth period, a first voltage is applied to the gate node of the fourth transistor, and

the first voltage is a voltage between a second voltage that turns on the fourth transistor and a third voltage that turns off the fourth transistor.

4. The display device according to claim 1 , wherein

the display element is an OLED having one end and another end, and the one end is coupled to the fourth transistor,

the first period includes a first initialization period, a second initialization period, and a third initialization period,

in the first initialization period, the second transistor is on state, the third transistor and the fourth transistor are off state, and a voltage that turns off the first transistor is applied to the gate node of the first transistor via the data line and the second transistor,

in the second initialization period, the second transistor is off state, the third transistor and the fourth transistor are on state, and a voltage that causes the OLED not to emit light is applied to one end of the display element via the data line, the third transistor, and the fourth transistor, and

in the third initialization period, the second transistor is on state, the third transistor and the fourth transistor are off state, and a voltage that turns on the first transistor is applied to the gate node of the first transistor via the data line.

5. An electronic apparatus comprising the display device according to claim 1 .

6. A display device comprising:

a data line;

a scanning line;

a display element provided corresponding to an intersection of the data line and the scanning line;

a first transistor configured to supply a current in accordance with a voltage between a gate and a source thereof to the display element;

a second transistor electrically coupled between the data line and the gate of the first transistor, the second transistor having a gate electrically coupled to the scanning line;

a third transistor electrically coupled between a drain of the first transistor and the data line; and

a fourth transistor electrically coupled between the first transistor and the display element, wherein

in a first period, the first transistor and the second transistor are off state, the third transistor and the fourth transistor are on state, and the data line and the display element are electrically coupled, and

in a second period, the first transistor, the second transistor and the third transistor are on state, the fourth transistor is off state, and the drain of the first transistor and the gate of the first transistor are electrically coupled.

7. The display device according to claim 6 , wherein

in the first period, a first potential that causes the display element to be in a non-light-emission state is supplied to the display element via the data line, and

in the second period, the same potential as that of a power supply line electrically coupled to the source of the first transistor is supplied to the data line.

8. The display device according to claim 7 , wherein

in a third period between the first period and the second period,

a second potential that is lower than potential of the power supply line is supplied to the data line, and

the first transistor, the third transistor and the fourth transistor are off state, the second transistor is on state, and the initial potential is supplied to the gate of the first transistor.

9. The display device according to claim 6 , wherein

in a third period between the first period and the second period,

a second potential that is lower than potential of a power supply line is supplied to the data line, and

the first transistor, the third transistor and the fourth transistor are off state, the second transistor is on state, and the initial potential is supplied to the gate of the first transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2021
From: KODAMA, TAKUMI; KOSHIHARA, TAKESHI
To: SEIKO EPSON CORPORATION
Reel/Frame 054936/0363 →
Priority Claims (1)
JP 2020-005726 · Jan 17, 2020 · national
Continuity (1)
Related Publication 20210225990A1 · Jul 22, 2021
Cited By (1)
US 12,315,465