Processing-in-memory (PIM) devices
A processing-in-memory (PIM) device includes a plurality of storage regions, a global buffer, and a plurality of multiplication/accumulation (MAC) circuits. The plurality of MAC circuits are configured to perform a MAC operation of first data from the plurality of storage regions and second data from the global buffer. Each of the plurality of MAC circuits is categorized as either an active MAC circuit or an inactive MAC circuit. The MAC operation includes a selective MAC operation which is selectively performed by the active MAC circuit.
1. A processing-in-memory (PIM) device comprising:
a plurality of storage regions;
a global buffer; and
a plurality of multiplication and accumulation (MAC) circuits configured to perform a MAC operation of first data from one of the plurality of storage regions and second data from the global buffer,
wherein each of the plurality of MAC circuits is categorized as one of an active MAC circuit and an inactive MAC circuit, and
wherein the MAC operation includes a selective MAC operation, the selective MAC operation is selectively performed by the active MAC circuit.
2. The PIM device of claim 1 , wherein each of the plurality of storage regions corresponds to a bank included in a dynamic random access memory (DRAM).
3. The PIM device of claim 1 , further comprising a mode register set (MRS) logic circuit configured to generate and output an MRS command including information for designating the active MAC circuit in response to an external command provided by an external device to request the MAC operation.
4. The PIM device of claim 3 , wherein the MRS command further includes information for designating an active storage region allocated to the active MAC circuit among the plurality of storage regions.
5. The PIM device of claim 4 , wherein the MRS logic circuit includes:
a mode register configured to store a MAC circuit identification having information for designating the active MAC circuit;
a control code generator configured to generate a control code including information on the active MAC circuit from the MAC circuit identification; and
an MRS command generator configured to generate the MRS command including information on the active MAC circuit and a request for the MAC operation according to the control code.
6. The PIM device of claim 5 , wherein the MAC circuit identification includes a plurality of bits corresponding to respective ones of the MAC circuits.
7. The PIM device of claim 6 , wherein the mode register further includes a bit for determining execution of the MAC operation.
8. The PIM device of claim 4 , further comprising a MAC command generator configured to receive the MRS command outputted from the MRS logic circuit and configured to generate and selectively transmit a MAC operation command to the active MAC circuit and the active storage region which are designated by the MRS command.
9. The PIM device of claim 8 , wherein the MAC operation command includes an active control signal for selectively activating the active storage region, a MAC read control signal for transmitting the first data stored in the active storage region to the active MAC circuit, and a MAC operation control signal for controlling the MAC operation of the active MAC circuit.
10. The PIM device of claim 9 , wherein the MAC command generator is configured to sequentially generate the active control signal, the MAC read control signal, and the MAC operation control signal.
11. The PIM device of claim 9 , wherein the MAC operation command further includes a pre-charge control signal for selectively pre-charging the active storage region.
12. The PIM device of claim 11 , wherein the MAC command generator is configured to sequentially generate the active control signal, the MAC read control signal, the MAC operation control signal, and the pre-charge control signal.
13. The PIM device of claim 1 , further comprising:
a global input and output (GIO) line providing a first data transmission path between the global buffer and each of the storage regions; and
bank input and output (BIO) lines, a BIO line from the BIO lines providing a second data transmission path between a storage from the storage regions and a MAC circuit, from the MAC circuits, allocated to the storage region.
14. The PIM device of claim 13 ,
wherein the first data are transmitted from the storage regions to the MAC circuits through the BIO lines; and
wherein the second data are transmitted from the global buffer to the MAC circuits through the GIO line.
15. The PIM device of claim 14 , wherein the first data and the second data are transmitted in a parallel transmission mode.