Semiconductor device and manufacturing method of the semiconductor device
A semiconductor device includes a stacked structure including conductive layers and gaps respectively interposed between the conductive layers, a channel layer passing through the stacked structure, a ferroelectric layer surrounding a sidewall of the channel layer, and first dielectric patterns interposed between the ferroelectric layer and the conductive layers, respectively. The gaps extending between the first dielectric patterns.
1. A semiconductor device, comprising:
a stacked structure including conductive layers and gaps respectively interposed between the conductive layers;
a channel layer passing through the stacked structure;
a ferroelectric layer surrounding a sidewall of the channel layer; and
first dielectric patterns interposed between the ferroelectric layer and the conductive layers, respectively,
wherein the gaps extend between the first dielectric patterns.
2. The semiconductor device of claim 1 , wherein the first dielectric patterns include a material having a larger band gap than the ferroelectric layer.
3. The semiconductor device of claim 1 , wherein the ferroelectric layer is interposed between the channel layer and the conductive layers and between the channel layer and the gaps.
4. The semiconductor device of claim 1 , wherein the ferroelectric layer includes ferroelectric patterns interposed between the channel layer and the conductive layers and separated from each other.
5. The semiconductor device of claim 4 , wherein the gaps extend between the ferroelectric patterns.
6. The semiconductor device of claim 1 , wherein each of the gaps comprises:
a first portion interposed between the conductive layers; and
a second portion protruding further toward the channel layer than the conductive layers.
7. The semiconductor device of claim 6 , wherein the second portion has a greater width than the first portion.
8. The semiconductor device of claim 6 , wherein the ferroelectric layer extends between second portions of the gaps.
9. The semiconductor device of claim 1 , further comprising a second dielectric layer interposed between the first dielectric patterns and the ferroelectric layer and including a material having a higher dielectric constant than the first dielectric patterns.
10. The sera conductor device of claim 1 , further comprising a second dielectric layer interposed between the first dielectric patterns and the ferroelectric layer and including a material having a larger band gap than the ferroelectric layer.
11. The semiconductor device of claim 1 , further comprising a third dielectric layer interposed between the ferroelectric layer and the channel layer and including a material having a higher dielectric constant than the first dielectric patterns.
12. The semiconductor device of claim 1 , further comprising a third dielectric layer interposed between the ferroelectric layer and the channel layer and including a material having a larger band gap than the ferroelectric layer.
13. The semiconductor device of claim 1 , wherein the ferroelectric layer includes grooves on a sidewall of the ferroelectric layer and the grooves are located at levels corresponding to the gaps.
14. The semiconductor device of claim 1 , wherein the gaps include a gas.
15. The semiconductor device of claim 1 , wherein the gaps include air.