Miniaturized transistor structure with controlled dimensions of source/drain and contact-opening and related manufacture method
View Patent ↗A transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first isolation region. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first isolation region is next to the first conductive region. A length of the first conductive region between the gate structure and the first isolation is controlled by a single photolithography process which is originally configured to define the length of the gate structure.
1. A transistor structure comprising:
a semiconductor substrate with a semiconductor surface;
a gate structure;
a channel region under the gate structure;
a first conductive region electrically coupled to the channel region; and
a contact hole positioned above the first conductive region;
wherein a length of the contact hole is less than a minimum feature length, and a horizontal distance between a sidewall of the gate structure and a sidewall of the contact hole which is remote from the gate structure is less than the minimum feature length or approximately equal to the minimum feature length.
2. A transistor structure comprising:
a semiconductor substrate with a semiconductor surface;
a gate structure with a length;
a channel region under the semiconductor surface;
a first isolation region extending upward and downward from the semiconductor surface;
a first spacer covering a first sidewall of the gate structure;
a first semiconductor region electrically coupled to the channel region and positioned between the gate structure and the first isolation region, wherein at least an external sidewall surface and a top surface of the first semiconductor region are contacted by a first metal zone; and
a first contact hole, wherein the first contact hole is formed between the first spacer and the first isolation region.
3. The transistor structure in claim 2 , further comprising:
a cap layer covering the gate structure;
wherein the first metal zone comprises a first metal region filling in the first contact hole and contacting the top surface of the first semiconductor region, the first metal zone further comprises a first metal containing region under the semiconductor surface and contacting the external sidewall surface of the first semiconductor region.
4. The transistor structure in claim 3 , further comprising a first guard layer isolating a bottom of the first semiconductor region and a bottom of the first metal containing region from the semiconductor substrate.
5. The transistor structure in claim 4 , wherein the first guard layer is an L shape oxide layer.
6. The transistor structure in claim 2 , further comprising:
a second isolation region extending upward and downward from the semiconductor surface; and
a second semiconductor region electrically coupled to the channel region and positioned between the gate structure and the second isolation region;
wherein at least one sidewall surface of the second semiconductor region is contacted by a second metal contacting region under the semiconductor surface.
7. The transistor structure in claim 6 , further comprising:
a second contact hole positioned above the second conductive region, wherein a length of the second contact hole is less than a minimum feature length, wherein a horizontal distance between a second sidewall surface of the gate structure and a sidewall surface of the second isolation region remote from the gate structure is substantially equal to the minimum feature length.
8. The transistor structure in claim 6 , further comprising:
a second guard layer isolating a bottom of the second semiconductor region from the semiconductor substrate, wherein the second guard layer does not isolate a bottom of the second metal contacting region from the semiconductor substrate.
9. A transistor structure comprising:
a semiconductor substrate with a semiconductor surface;
a gate structure with a length;
a channel region;
a first conductive region electrically coupled to the channel region; and
a first isolation region next to the first conductive region;
wherein a length of the first conductive region is controlled by a single photolithography process which is originally configured to define the length of the gate structure.
10. The transistor structure in claim 9 , wherein a length of the first conductive region is equal to or substantially equal to a minimum feature length.
11. A transistor structure comprising:
a semiconductor substrate with a semiconductor surface;
a gate structure with a length;
a channel region;
a first conductive region electrically coupled to the channel region; and
a first contact hole;
wherein a length of the first conductive region is equal to or substantially equal to the a minimum feature length, wherein the minimum feature length is not greater than 28 nm.
12. The transistor structure in claim 11 , wherein a length of the first contact hole is less than the minimum feature length.
13. The transistor structure in claim 11 , wherein the first contact hole is positioned above the first conductive region.