SRAM structures

1. A Static Random Access Memory (SRAM) array, comprising:

a first subarray including a plurality of first SRAM cells;

a second subarray including a plurality of second SRAM cells; and

a word line spanning over the first subarray and the second subarray and electrically coupled to at least one of the plurality of first SRAM cells and at least one of the plurality of second SRAM cells,

wherein each n-type transistor in the plurality of first SRAM cells includes a first work function stack,

wherein each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.

2. The SRAM array of claim 1 , wherein a threshold voltage of each n-type transistor in the plurality of first SRAM cells is smaller than a threshold voltage of each n-type transistor in the plurality of second SRAM cells.

3. The SRAM array of claim 1 ,

wherein each p-type transistor in the plurality of first SRAM cells includes the second work function stack,

wherein each p-type transistor in the plurality of second SRAM cells includes the first work function stack.

4. The SRAM array of claim 3 , wherein a threshold voltage of each p-type transistor in the plurality of first SRAM cells is greater than a threshold voltage of each p-type transistor in the plurality of second SRAM cells.

5. The SRAM array of claim 3 ,

wherein the first work function stack includes a titanium aluminum layer

wherein the second work function stack includes at least one titanium nitride layer and the titanium aluminum layer disposed over the at least one titanium nitride layer.

6. The SRAM array of claim 1 ,

wherein the first subarray is disposed at a corner of the SRAM array and the second subarray surrounds the first subarray.

7. The SRAM array of claim 1 ,

wherein the SRAM array comprises a plurality of word lines extending along a first direction and a plurality of bit lines extending along a second direction perpendicular to the first direction,

wherein the SRAM array has a length along the first direction and a width along the second direction.

8. The SRAM array of claim 7 ,

wherein the first subarray is parallel to the second subarray, and

wherein both the first subarray and the second subarray extend an entirety of the length of the SRAM array.

9. The SRAM array of claim 7 ,

wherein the first subarray is parallel to the second subarray, and

wherein both the first subarray and the second subarray extend an entirety of the width of the SRAM array.

10. A memory device, comprising:

a Static Random Access Memory (SRAM) array comprising:

a first subarray including a plurality of first SRAM cells, and

a second subarray including a plurality of second SRAM cells; and

a word line driver coupled to the plurality of first SRAM cells and the plurality of second SRAM cells via a plurality of word lines extending along a first direction,

wherein each n-type transistor in the plurality of first SRAM cells includes a first work function stack,

wherein each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack,

wherein each p-type transistor in the plurality of first SRAM cells includes the second work function stack,

wherein each p-type transistor in the plurality of second SRAM cells includes the first work function stack,

wherein a thickness of the second work function stack is greater than a thickness of the first work function stack,

wherein a word line of the plurality of word lines spans over the first subarray and the second subarray and is electrically coupled to at least one of the plurality of first SRAM cells and at least one of the plurality of second SRAM cells.

11. The memory device of claim 10 ,

wherein the first work function stack includes a titanium aluminum layer

wherein the second work function stack includes at least one titanium nitride layer and the titanium aluminum layer disposed over the at least one titanium nitride layer.

12. The memory device of claim 10 , further comprising:

a read/write block coupled to the plurality of first SRAM cells and the plurality of second SRAM cells via a plurality of bit lines extending along a second direction perpendicular to the first direction,

wherein each n-type transistor in the word line driver and the read/write block comprises a third work function stack different from the first work function stack or the second work function stack.

13. The memory device of claim 12 , wherein the third work function stack is thinner than the second work function stack and thicker than the first work function stack.

14. The memory device of claim 10 , further comprising:

a word line driver coupled to the plurality of first SRAM cells and the plurality of second SRAM cells via a plurality of word lines,

wherein the word line driver comprises a high-speed region and a standard region,

wherein each n-type transistor in the high-speed region includes the first work function stack,

wherein each n-type transistor in the standard region includes a third work function stack different from the first work function stack or the second work function stack.

15. The memory device of claim 10 , further comprising:

a read/write block coupled to the plurality of first SRAM cells and the plurality of second SRAM cells via a plurality of bit lines,

wherein the read/write block comprises a high-speed block and a standard block,

wherein each n-type transistor in the high-speed block includes the first work function stack,

wherein each n-type transistor in the standard block includes a third work function stack different from the first work function stack or the second work function stack.

16. A memory device, comprising:

a Static Random Access Memory (SRAM) array comprising:

a first subarray including a plurality of first SRAM cells, and

a second subarray including a plurality of second SRAM cells;

a word line driver coupled to the plurality of first SRAM cells and the plurality of second SRAM cells via a plurality of word lines extending along a first direction; and

a read/write block coupled to the plurality of first SRAM cells and the plurality of second SRAM cells via a plurality of bit lines extending along a second direction perpendicular to the first direction,

wherein each n-type transistor in the plurality of first SRAM cells includes a first work function stack,

wherein each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack,

wherein each p-type transistor in the plurality of first SRAM cells includes the second work function stack,

wherein each p-type transistor in the plurality of second SRAM cells includes the first work function stack,

wherein the first work function stack includes a titanium aluminum layer,

wherein the second work function stack includes at least one titanium nitride layer and the titanium aluminum layer disposed over the at least one titanium nitride layer,

wherein a word line of the plurality of word lines spans over the first subarray and the second subarray and is electrically coupled to at least one of the plurality of first SRAM cells and at least one of the plurality of second SRAM cells.

17. The memory device of claim 16 ,

wherein the word line driver includes a first portion and a second portion,

wherein the plurality of word lines include a first plurality of word lines and a second plurality of word lines,

wherein the first portion is coupled to the first subarray via the first plurality of word lines,

wherein the second portion is coupled to the second subarray via the second plurality of word lines

wherein each n-type transistor in the first portion includes the first work function stack, and

wherein each n-type transistor in the second portion includes the second work function stack.

18. The memory device of claim 16 ,

wherein the read/write block includes a first block and a second block,

wherein the plurality of bit lines include a first plurality of bit lines and a second plurality of bit lines,

wherein the first block is coupled to the first subarray via the first plurality of bit lines,

wherein the second block is coupled to the second subarray via the second plurality of bit lines

wherein each n-type transistor in the first block includes the first work function stack, and

wherein each n-type transistor in the second block includes a third work function stack different from the first work function stack or the second work function stack.

19. The memory device of claim 16 , wherein the first subarray is disposed farther away from the word line driver than the second subarray.

20. The memory device of claim 16 , wherein the first subarray is disposed farther away from the read/write block than the second subarray.