Power supply device and pulse frequency modulation method
A power supply device includes a pulse frequency modulation controller circuitry and a cycle controller circuitry. The pulse frequency modulation controller circuitry is configured to adjust a transiting speed of a first signal according to at least one control bit, and to compare the first signal with a first reference voltage to generate a second signal, and to generate a driving signal to a power converter circuit according to an output voltage, a second reference voltage, and the second signal, in which the power converter circuit is configured to generate the output voltage according to the driving signal. The cycle controller circuitry is configured to detect a frequency of the driving signal according to a clock signal having a predetermined frequency, in which the predetermined frequency is set based on a frequency range capable of being heard by humans.
1. A power supply device, comprising:
a pulse frequency modulation controller circuitry configured to adjust a capacitance value of a node that outputs a first signal according to at least one control bit to adjust a transiting speed of the first signal, and to compare the first signal with a first reference voltage to generate a second signal, and to generate a driving signal to a power converter circuit according to an output voltage, a second reference voltage, and the second signal, wherein the power converter circuit is configured to generate the output voltage according to the driving signal; and
a cycle controller circuitry configured to detect a frequency of the driving signal according to a clock signal having a predetermined frequency, wherein the predetermined frequency is set based on a frequency range capable of being heard by humans.
2. The power supply device of claim 1 , wherein the cycle controller circuitry is configured to adjust the at least one control bit, in order to prevent the frequency of the driving signal from falling within the frequency range capable of being heard by humans.
3. The power supply device of claim 1 , wherein the pulse frequency modulation controller circuitry comprises:
a switched-capacitor array circuit configured to determine the capacitance value of the node according to the at least one control bit;
a first switch configured to be turned on according to an enable signal to output a current signal, in order to charge the node to generate the first signal;
a second switch configured to be selectively turned on according to the driving signal, in order to reset a level of the node;
a comparator circuit configured to compare the first reference voltage with the first signal, in order to generate a third signal; and
an inverter circuit configured to generate the second signal according to the third signal.
4. The power supply device of claim 3 , wherein the switched-capacitor array circuit comprises:
at least one capacitor; and
at least one third switch coupled between the at least one capacitor and the node, wherein each of the at least one third switch is configured to be turned on according to a corresponding one of the at least one control bit.
5. The power supply device of claim 1 , wherein the pulse frequency modulation controller circuitry comprises:
a comparator circuit configured to compare the output voltage with the second reference voltage, in order to generate a set signal;
a SR latch circuit configured to generate an enable signal according to the set signal and the second signal; and
an inverter circuit configured to generate the driving signal according to the enable signal.
6. The power supply device of claim 5 , wherein the SR latch circuit comprises a plurality of NOR gate circuits or a plurality of NAND gate circuit.
7. The power supply device of claim 1 , wherein the cycle controller circuitry is configured to count a number of pulses in the driving signal during a period of the clock signal, in order to generate a count value, and to adjust the at least one control bit according to the count value.
8. The power supply device of claim 7 , wherein if the count value is zero, the cycle controller circuitry is configured to adjust the at least one control bit, in order to increase the transiting speed of the first signal.
9. The power supply device of claim 7 , wherein if the count value is greater than or equal to a default value, the cycle controller circuitry is configured to adjust the at least one control bit during the period of the clock signal, in order to decrease the transiting speed of the first signal.
10. The power supply device of claim 7 , wherein if the count value is greater than or equal to a default value, the cycle controller circuitry is configured to adjust the at least one control bit during a next period of the clock signal, in order to decrease the transiting speed of the first signal.
11. The power supply device of claim 1 , wherein the predetermined frequency is higher than a highest frequency in the frequency range capable of being heard by humans.
12. A pulse frequency modulation method, comprising:
adjusting a capacitance value of a node that outputs a first signal according to at least one control bit to adjust a transiting speed of the first signal, and comparing the first signal with a first reference voltage, in order to generate a second signal;
generating a driving signal to a power converter circuit according to an output voltage, a second reference voltage, and the second signal, wherein the power converter circuit is configured to generate the output voltage according to the driving signal; and
detecting a frequency of the driving signal according to a clock signal having a predetermined frequency, in order to adjust the at least one control bit, wherein the predetermined frequency is set based on a frequency range capable of being heard by humans.
13. The pulse frequency modulation method of claim 12 , wherein the at least one control bit is adjusted to prevent the frequency of the driving signal from falling within the frequency range capable of being heard by humans.
14. The pulse frequency modulation method of claim 12 , wherein adjusting the capacitance value of the node that outputs the first signal according to the at least one control bit to adjust the transiting speed of the first signal, and comparing the first signal with the first reference voltage, in order to generate the second signal comprises:
controlling a switched-capacitor array circuit according to the at least one control bit, in order to determine the capacitance value of the node;
outputting a current signal according to an enable signal, in order to charge the node to generate the first signal;
selectively setting a level of the node according to the driving signal;
comparing with the first reference voltage with the first signal, in order to generate a third signal; and
generating the second signal according to the third signal, wherein the third signal and the second signal have opposite logic values.
15. The pulse frequency modulation method of claim 12 , wherein generating the driving signal to the power converter circuit according to the output voltage,
the second reference voltage, and the second signal comprises:
comparing the output with the second reference voltage, in order to generate a set signal;
generating, by a SR latch circuit, an enable signal according to the set signal and the second signal; and
generating the driving signal according to the enable signal, wherein the enable signal and the driving signal have opposite logic values.
16. The pulse frequency modulation method of claim 12 , wherein detecting the frequency of the driving signal according to the clock signal having the predetermined frequency, in order to adjust the at least one control bit comprises:
counting a number of pulses in the driving signal during a period of the clock signal, in order to generate a count value, and adjusting the at least one control bit according to the count value.
17. The pulse frequency modulation method of claim 16 , wherein adjusting the at least one control bit according to the count value comprises:
if the count value is greater than or equal to a default value, adjusting the at least one control bit during the period, in order to decrease the transiting speed of the first signal.
18. The pulse frequency modulation method of claim 16 , wherein adjusting the at least one control bit according to the count value comprises:
if the count value is greater than or equal to a default value, adjusting the at least one control bit during a next period of the clock signal, in order to decrease the transiting speed of the first signal.
19. The pulse frequency modulation method of claim 16 , wherein adjusting the at least one control bit according to the count value comprises:
if the count value is zero, adjusting the at least one control bit, in order to increase the transiting speed of the first signal.
20. The pulse frequency modulation method of claim 12 , wherein the predetermined frequency is higher than a highest frequency in the frequency range capable of being heard by humans.