Semiconductor device and method of manufacture

1. A method of manufacturing a semiconductor device, the method comprising:

forming a recess between a first semiconductor fin and a second semiconductor fin;

depositing a first liner to line the recess, the first liner comprising a first material;

annealing the first liner to transform the first material to a second material, wherein the annealing the first liner comprises a first wet anneal at a first temperature;

depositing a second liner to line the recess, the second liner comprising a third material; and

annealing the second liner to transform the third material to a fourth material.

2. The method of claim 1 , wherein the first material comprises silicon oxynitride and the second material comprises silicon dioxide.

3. The method of claim 2 , wherein the third material comprises silicon oxycarbonitride and the fourth material comprises silicon dioxide.

4. The method of claim 3 , wherein the annealing the first liner comprises:

performing a second wet anneal at a second temperature different from the first temperature; and

performing a first dry anneal.

5. The method of claim 4 , wherein the annealing the second liner comprises:

performing a third wet anneal at a third temperature;

performing a fourth wet anneal at a fourth temperature different from the third temperature; and

performing a second dry anneal.

6. The method of claim 1 , wherein the depositing the first liner comprises:

pulsing hexachlorodisilane onto the first semiconductor fin;

pulsing oxygen onto the first semiconductor fin after the pulsing the hexachlorodisilane; and

pulsing ammonia onto the first semiconductor fin after the pulsing the oxygen.

7. The method of claim 1 , wherein the depositing the second liner comprises:

pulsing hexachlorodisilane onto the first semiconductor fin;

pulsing triethylamine onto the first semiconductor fin after the pulsing the hexachlorodisilane; and

pulsing oxygen onto the first semiconductor fin after the pulsing the triethylamine.

8. A semiconductor device comprising:

a first semiconductor fin and a second semiconductor fin over a semiconductor substrate;

a first liner adjacent to both the first semiconductor fin and the second semiconductor fin;

a second liner over the first liner;

a third liner over the second liner, the third liner comprising nitrogen at a percentage of less than about 10%;

a fourth liner over the third liner;

a capping layer over the fourth liner, the capping layer comprising carbon at a percentage of less than about 10%; and

a dielectric cap over the capping layer, wherein the first semiconductor fin extends further away from the semiconductor substrate than the dielectric cap.

9. The semiconductor device of claim 8 , wherein the capping layer has a thickness of between about 10 Å and about 70 Å.

10. The semiconductor device of claim 8 , wherein the third liner has a thickness of between about 10 Å and about 50 Å.

11. The semiconductor device of claim 8 , wherein the second liner comprises silicon dioxide.

12. The semiconductor device of claim 8 , wherein the capping layer comprises silicon dioxide.

13. The semiconductor device of claim 8 , wherein the first liner is silicon.

14. A semiconductor device comprising:

a first semiconductor fin adjacent to a second semiconductor fin, the first semiconductor fin over a semiconductor substrate;

a first isolation region extending from a first sidewall of the first semiconductor fin to a second sidewall of the second semiconductor fin, the first isolation region comprising:

a first liner extending from the first semiconductor fin to the second semiconductor fin, the first liner comprising a first material;

a second liner over the first liner, the second liner comprising a second material;

a third liner over the second liner, the third liner comprising a third material, the third material have nitrogen at a percentage of less than about 10%;

a fourth liner over the third liner, the fourth liner comprising a fourth material;

a capping layer over the fourth liner, the capping layer comprising a capping material, the capping material comprising carbon at a percentage of less than about 10%; and

a dielectric cap over the capping layer, wherein the first isolation region has a top surface closer to the semiconductor substrate than the first semiconductor fin; and

a second isolation region adjacent to the first semiconductor fin, the second isolation region comprising:

a fifth liner adjacent to the first semiconductor fin, the fifth liner comprising the first material;

a sixth liner over the fifth liner, the sixth liner comprising the second material;

a seventh liner over the sixth liner, the seventh liner comprising the third material;

an eighth liner over the seventh liner, the eighth liner comprising the fourth material;

a second capping layer over the eighth liner, the second capping layer comprising the capping material;

a second dielectric cap over the second capping layer; and

a dielectric fin extending into at least the second dielectric cap, a portion of the dielectric fin being planar with the first semiconductor fin, wherein there is no dielectric fin extending into the first isolation region.

15. The semiconductor device of claim 14 , wherein the capping layer has a thickness of between about 10 Å and about 70 Å.

16. The semiconductor device of claim 14 , wherein the third liner has a thickness of between about 10 Å and about 50 Å.

17. The semiconductor device of claim 14 , wherein the second liner comprises silicon dioxide.

18. The semiconductor device of claim 14 , wherein the capping layer comprises silicon dioxide.

19. The semiconductor device of claim 14 , wherein the first liner is silicon.

20. The semiconductor device of claim 14 , wherein the first semiconductor fin is separated from the second semiconductor fin by a distance of between about 5 nm and about 30 nm.