Roughened conductive components

1. A semiconductor package, comprising:

a die pad;

a semiconductor die on the die pad;

a mold compound covering the die pad and the semiconductor die;

a conductive component including a roughened surface, the roughened surface having a roughness ranging from an arithmetic mean surface height (SA) of 1.4 to 3.2, the mold compound coupled to the roughened surface; and

a bond wire coupling the semiconductor die to the roughened surface, the bond wire directly coupled to the roughened surface without a precious metal positioned therebetween.

2. The semiconductor package of claim 1 , wherein at least some of the mold compound is positioned within an orifice in the roughened surface.

3. The semiconductor package of claim 1 , wherein the bond wire fills an orifice in the roughened surface and covers a protrusion of the roughened surface.

4. The semiconductor package of claim 1 , wherein the roughened surface is an etched surface.

5. The semiconductor package of claim 1 , wherein the roughened surface is a copper-plated surface.

6. The semiconductor package of claim 1 , wherein the roughened surface comprises copper.

7. The semiconductor package of claim 1 , wherein the roughened surface comprises a copper-iron alloy.

8. A semiconductor package, comprising:

a conductive component including a roughened surface having a roughness ranging from an arithmetic mean surface height (SA) of 1.4 to 3.2, the roughened surface including an orifice and a protrusion; and

a bond wire directly coupled to the roughened surface, wherein a position of the bond wire fills the orifice and covers the protrusion without a precious metal positioned between the bond wire and the roughened surface.

9. The semiconductor package of claim 8 , wherein the roughened surface is an etched surface.

10. The semiconductor package of claim 8 , wherein the roughened surface is a copper-plated surface.

11. The semiconductor package of claim 10 , wherein the conductive component comprises a copper-iron alloy.

12. A semiconductor package, comprising:

a copper-iron alloy surface having a first etched or copper-plated area and a second etched or copper-plated area;

a semiconductor die disposed over the first etched or copper-plated area;

a mold compound covering the copper-iron alloy surface and filling an orifice in the first etched or copper-plated area; and

a bond wire directly coupled to the second etched or copper-plated area without a precious metal positioned therebetween.

13. The semiconductor package of claim 12 , wherein the first and second etched or copper-plated areas have a roughness ranging from an arithmetic mean surface height (SA) of 1.4 to 3.2.

14. A method for manufacturing a semiconductor package, comprising:

coupling a semiconductor die to a die pad; and

coupling a bond wire to the semiconductor die and to a roughened surface of a conductive component using a thermosonic technique including:

applying heat to the roughened surface to cause an anti-tarnish chemical coat abutting the roughened surface to decompose;

causing the decomposed anti-tarnish chemical coat to slough off of the roughened surface using at least one of mechanical and ultrasonic energy; and

causing the bond wire to adhere directly to the roughened surface without a precious metal positioned therebetween.

15. The method of claim 14 , wherein the anti-tarnish chemical coat includes benzotriazole or an organic film.

16. The method of claim 14 , wherein the anti-tarnish chemical coat follows a topography of the roughened surface.

17. A semiconductor package, comprising:

a die pad having a roughened surface with a roughness ranging from an arithmetic mean surface height (SA) of 1.4 to 3.2;

an anti-tarnish chemical coat abutting the roughened surface;

a semiconductor die on the anti-tarnish chemical coat; and

a mold compound covering the semiconductor die.

18. The semiconductor package of claim 17 , wherein the semiconductor package lacks a precious metal plating between the die pad and the semiconductor die.

19. The semiconductor package of claim 17 , wherein the anti-tarnish chemical coat follows a topography of the roughened surface.

20. The semiconductor package of claim 17 , further comprising a lead having a plated or etched surface with a roughness ranging from an SA of 1.4 to 3.2.