MEMORY MODULE WITH BUFFERED MEMORY PACKAGES
A DRAM package is operable on a memory module communicatively coupled to a system memory controller. The memory module includes a register device configurable to receive input command/address signals from the system memory controller and to output buffered command/address signals and data path control signals. The DRAM package includes stacked array dies and a control die. The control die includes data buffers, and is configurable to provide at least some of the buffered command/address signals to the stacked array dies, and to control the data buffers in response to the data path control signals to buffer data signals communicated between a selected array die of the stacked array dies and the system memory controller.
1 . A DRAM package operable on a memory module communicatively coupled to a system memory controller via a command/address bus and a data bus, the memory module including a register device, the DRAM package comprising:
terminals including control terminals coupled to the register device and data terminals to be coupled to a respective section of the data bus, the register device being configurable to receive input command/address signals from the system memory controller via the command/address bus and to output buffered command/address signals and data path control signals, the control terminals including first control terminals via which the DRAM package receives the buffered command/address signals and second control terminals via which the DRAM package receives the data path control signals;
stacked array dies; and
a control die coupled between the stacked array dies and the terminals, the control die including data buffers and a data path control circuit, and configurable to:
provide at least some of the buffered command/address signals to the stacked array dies, including providing respective chip-select signals to respective array dies of the stacked array dies; and
control the data buffers in response to the data path control signals to buffer data signals communicated between a selected array die of the stacked array dies and the respective section of the data bus, the selected array die having received one of the chip select signals that is different from any of the other ones of the chip select signals.