IP Library Granted Patent US 11,723,223
Granted Patent B2
US 11,723,223 · App. 17/158,367 · Granted Aug 8, 2023

Low-noise integrated post-processed photodiode

Inventor: Robert Daniel McGrath (Lexington, MA)
Assignee: BAE Systems Imaging Solutions Inc.
H10K39/32H01L27/14612H01L27/14636H01L27/14643H01L27/1463H01L27/14689H10K30/82
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Quick Facts
Patent No.
US 11,723,223
App. No.
17/158,367
Granted
Aug 8, 2023
Kind
B2
Abstract

A pixel, is provided the pixel comprising: a photodiode structure built on top of an integrated circuit generating a charge; the integrated circuit comprising at least one semiconductor material and at least one interconnect layer; the at least one interconnect layer comprises an interconnect to facilitate charge flowing into a collection node disposed in the semiconductor material; the interconnect being in contact with a doped contact diffusion disposed proximate to the collection node; a transfer transistor disposed between the collection node and a conversion node, the conversion node coupled to an active transistor; the pixel having a reset configured to reset the conversion node.

Claims (40)

1. A sensor, said sensor comprising:

an array of pixels;

at least one pixel in said array comprising a photodiode structure built on top of an integrated circuit generating a charge;

said integrated circuit comprising at least one semiconductor material and at least one interconnect layer;

said at least one interconnect layer comprising an interconnect to facilitate said charge flowing into a collection node disposed in said semiconductor material;

said interconnect being in contact with a doped contact diffusion disposed within said collection node;

a transfer transistor disposed between said collection node and a conversion node, said conversion node coupled to an active transistor;

each said at least one pixel having a reset configured to reset said conversion node;

at least one bias circuit providing bias to said array;

at least one clock circuit providing clocking to said array; and

at least one signal chain circuit detecting a signal output by at least one pixel of said array.

2. The sensor of claim 1 where said integrated circuit is built in a metal oxide semiconductor (MOS) process.

3. The sensor of claim 1 wherein said integrated circuit is built in a complementary metal oxide semiconductor (CMOS) process.

4. The sensor of claim 1 , wherein said doped contact diffusion is doped to a degree that it forms a layer that is conductive under operation.

5. The sensor of claim 1 wherein said doped contact diffusion isolates said collection node from defects in an interface between said at least one interconnect layer and said at least one semiconductor material.

6. The sensor of claim 1 , wherein said at least one interconnect layer comprises a plurality of interconnect layers selected from the group of layers consisting of a dielectric layer and a conductive layer.

7. The sensor of claim 1 , wherein said reset enables use of correlated double sampling.

8. The sensor of claim 1 , wherein said photodiode structure comprises at least one organic material.

9. The sensor of claim 8 , wherein said at least one organic material contains a suspension of photoactive material.

10. The sensor of claim 1 , wherein said interconnect comprises a metal.

11. The sensor of claim 1 , wherein the semiconductor material has a same doping type as the collection node.

12. A system, comprising:

an array of pixels;

at least one pixel in said array comprising a photodiode structure built on top of an integrated circuit generating a charge, said integrated circuit built in a complementary metal oxide semiconductor (CMOS) process;

said integrated circuit comprising at least one semiconductor material and at least one interconnect layer;

said at least one interconnect layer comprising an interconnect to facilitate said charge flowing into a collection node disposed in said semiconductor material;

said interconnect being in contact with a doped contact diffusion disposed within said collection node;

a transfer transistor disposed between said collection node and a conversion node, said conversion node coupled to an active transistor;

each said at least one pixel having a reset configured to reset said conversion node;

at least one bias circuit providing bias to said array;

at least one clock circuit providing clocking to said array; and

at least one signal chain circuit detecting a signal output by at least one pixel of said array.

13. The system of claim 12 , wherein the contact diffusion serves as a pinning layer.

14. The system of claim 12 , wherein said doped contact diffusion is doped to a degree that it forms a layer that is conductive under operation.

15. The system of claim 12 , wherein said doped contact diffusion isolates said collection node from defects in an interface between said at least one interconnect layer and said at least one semiconductor material.

16. The system of claim 12 , wherein said at least one interconnect layer comprises a plurality of interconnect layers selected from the group of layers consisting of a dielectric layer and a conductive layer.

17. The system of claim 12 , wherein said reset enables use of correlated double sampling.

18. The system of claim 12 , wherein said photodiode structure comprises at least one organic material.

19. The system of claim 12 , wherein said interconnect comprises a metal.

20. The system of claim 12 , wherein the semiconductor material has a same doping type as the collection node.

Assignments (2)
CHANGE OF NAME Recorded Dec 6, 2024
From: BAE SYSTEMS IMAGING SOLUTIONS INC.
To: FAIRCHILD IMAGING, INC.
Reel/Frame 069531/0646 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2021
From: MCGRATH, ROBERT D
To: BAE SYSTEMS IMAGING SOLUTIONS INC.
Reel/Frame 055032/0086 →
Continuity (2)
Division 16198247 · Nov 21, 2018
Related Publication 20210175288A1 · Jun 10, 2021