Semiconductor memory device, memory system, and write method

1. A memory system comprising:

a semiconductor memory device having a first memory region including a first memory cell capable of holding at least 4-bit data and a second memory region including a plurality of second memory cells capable of holding at least 1-bit data; and

a controller configured to control a first write operation and a second write operation based on the 4-bit data in the semiconductor memory device,

wherein the controller includes a conversion circuit which converts the 4-bit data into 2-bit data,

the semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted 2-bit data and data written in the first memory cell by the first write operation,

when the controller detects power shutdown, the conversion circuit converts the 4-bit data used for the first write operation into the 2-bit data, and

the controller instructs the semiconductor memory device to write each of the 2-bit data in different second memory cells of the plurality of second memory cells.

2. The system according to claim 1 , wherein

after power recovery, the controller instructs the semiconductor memory device to perform read operation of the 2-bit data written in the second memory region, recovery operation of the 4-bit data, and the second write operation.

3. The system according to claim 1 , wherein

a threshold voltage of the first memory cell is included in any one of a plurality of threshold distributions corresponding to the 4-bit data, and

assignment of the 2-bit data to the plurality of threshold distributions is different by 1 bit between the threshold distributions adjacent to each other.

4. A semiconductor memory device comprising:

a memory cell array including a first memory cell capable of holding at least 4-bit data; and

a conversion circuit configured to recover the 4-bit data based on 2-bit data generated by converting the 4-bit data and data written in the first memory cell,

wherein an operation of writing the 4-bit data in the first memory cell includes a first write operation and a second write operation,

the first write operation is executed based on the 4-bit data received from the outside, and

the second write operation is executed based on the 4-bit data recovered by the conversion circuit.

5. The device according to claim 4 , wherein

after the first write operation, the conversion circuit converts the 4-bit data into the 2-bit data, the converted 2-bit data is outputted to the outside, and

before the second write operation, the conversion circuit recovers the 4-bit data based on the 2-bit data received from the outside and the data read from the first memory cell.

6. The device according to claim 4 , wherein

the memory cell array further includes a plurality of second memory cells capable of holding at least 1-bit data,

each of the 2-bit data are written in different second memory cells of the plurality of second memory cells, and

before the second write operation, the conversion circuit recovers the 4-bit data based on the 2-bit data read from the second memory cells and the data read from the first memory cell.

7. A semiconductor memory device comprising:

a semiconductor substrate;

a first block including a first memory string including a plurality of first memory cells coupled in series;

a plurality of first word lines respectively coupled to the plurality of first memory cells; and

a first row decoder including a plurality of first transistors provided on a first well region formed on the semiconductor substrate and to which the plurality of first word lines are respectively coupled,

wherein in an erase operation of the first block, a first voltage that is a negative voltage is applied to the first well region, and a second voltage that is a negative voltage and is equal to or higher than the first voltage is applied to the plurality of first word lines.

8. The device according to claim 7 , further comprising:

a second block including a second memory string including a plurality of second memory cells coupled in series;

a plurality of second word lines respectively coupled to the plurality of second memory cells; and

a second row decoder including a plurality of second transistors provided on a second well region formed on the semiconductor substrate and to which the plurality of second word lines are respectively coupled,

wherein in the erase operation of the first block, a third voltage that is higher than the first voltage is applied to the second well region.

9. The device according to claim 7 , wherein

in a read operation of the first block, a fourth voltage that is a negative voltage is applied to the first well region, and a fifth voltage that is a negative voltage and is equal to or higher than the fourth voltage is applied to any one of the word lines.

10. The device according to claim 7 , wherein

in a write operation of the first block, a sixth voltage that is a negative voltage is applied to the first well region.

11. A semiconductor memory device comprising:

a semiconductor substrate;

a memory cell allay including a memory string including a plurality of memory cells coupled in series;

a plurality of word lines respectively coupled to the plurality of memory cells;

a bit line coupled to the memory string; and

a sense amplifier including a first transistor provided on a first well region formed on the semiconductor substrate and coupled to the bit line,

wherein in a write operation for a selected memory cell of the plurality of memory cells, a first voltage that is a negative voltage is applied to the first well region,

when writing is performed on one of the plurality of memory cells, a second voltage that is a negative voltage and equal to or higher than the first voltage is applied to the bit line, and

when non-writing is performed on one of the plurality of memory cells, a third voltage higher than the second voltage is applied to the bit line.

12. The device according to claim 11 , wherein

in the write operation, a program loop including a program operation and a program verify operation is repeated, when a program loop count is less than a first set count, a fourth voltage higher than the first voltage is applied to the first well region, and when the program loop count is equal to or higher than the first set count, the first voltage is applied to the first well region.

13. The device according to claim 11 , wherein

in the write operation, a program loop including a program operation and a program verify operation is repeated, when a program loop count is less than a first set count, a fourth voltage higher than the first voltage is applied to the first well region, and when the program loop count is equal to or higher than the first set count, a voltage of the first well region is stepped down from the fourth voltage each time the program loop is repeated.

14. The device according to claim 11 , further comprising

a row decoder including a plurality of second transistors provided on a second well region formed on the semiconductor substrate and respectively coupled to the plurality of word lines,

wherein in a read operation, a fifth voltage that is a negative voltage is applied to the second well region.

15. The device according to claim 11 , further comprising

a row decoder including a plurality of second transistors provided on a second well region formed on the semiconductor substrate and respectively coupled to the plurality of word lines,

wherein in the write operation, a fifth voltage that is a negative voltage is applied to the second well region.

16. A semiconductor memory device comprising:

a memory cell array including a first memory cell, a threshold voltage of the first memory cell being changeable among at least three levels, the at least three levels including a first level, a second level higher than the first level, and a third level higher than the second level;

a first word line connected to a gate of the first memory cell; and

a sequencer configured to perform a read operation on the first memory cell,

wherein,

when the read operation is performed on the first memory cell to read 1-bit data under a first condition,

a first read voltage, which is higher than the first level and lower than the second level is supplied to the first word line, and

when the read operation is performed on the first memory cell to read 1-bit data under a second condition,

a second read voltage, which is higher than the second level and lower than the third level is supplied to the first word line.

17. The semiconductor memory device according to claim 16 , wherein

the threshold voltage of the first memory cell being changeable among at least five levels, the at least five levels including the first level, the second level, the third level, a fourth level higher than the third level, and a fifth level higher than the fourth level,

when the read operation is performed on the first memory cell to read 1-bit data under a third condition,

a third read voltage, which is higher than the third level and lower than the fourth level is supplied to the first word line, and

when the read operation is performed on the first memory cell to read 1-bit data under a fourth condition,

a fourth read voltage, which is higher than the fourth level and lower than the fifth level is supplied to the first word line.

18. The semiconductor memory device according to claim 16 , wherein

the read operation under the first condition is performed after an erase operation, and

the read operation under the second condition is performed after the read operation under the first condition.

19. The semiconductor memory device according to claim 18 , wherein

between a time when the read operation under the first condition is performed and a time when the read operation under the second condition is performed, a pseudo erase operation is performed on the first memory cell.

20. The semiconductor memory device according to claim 16 , wherein

the read operation under the first condition is performed by supplying only one level of the first read voltage to the first word line, and

the read operation under the second condition is performed by supplying only one level of the second read voltage to the first word line.

21. The semiconductor memory device according to claim 16 , wherein

the first memory cell is provided in plurality,

the word line is connected to gates of the first memory cells,

when the read operation under the first condition is performed, a part of the first memory cells have threshold voltages corresponding to the first level, and the remaining part of the first memory cells have threshold voltages corresponding to the second level, and

when the read operation under the second condition is performed, a part of the first memory cells have threshold voltages corresponding to the first level, another part of the first memory cells have threshold voltages corresponding to the second level, and the remaining part of the first memory cells have threshold voltages corresponding to the third level.

22. The semiconductor memory device according to claim 16 , wherein

the sequencer is configured to receive a first read command and a second read command,

the read operation under the first condition is performed upon receipt of the first read command, and

the read operation under the second condition is performed upon receipt of the second read command.

23. The semiconductor memory device according to claim 16 , wherein

the memory cell array further includes a flag memory cell,

the read operation under the first condition is performed when a threshold voltage of the flag memory cell corresponds to the first level, and

the read operation under the second condition is performed when the threshold voltage of the flag memory cell corresponds to the second level or the third level.

24. The semiconductor memory device according to claim 17 , wherein

the memory cell array further includes a first flag memory cell, a second flag memory cell and a third flag memory cell,

the read operation under the first condition is performed when a threshold voltage of the first flag memory cell corresponds to the first level,

the read operation under the second condition is performed when the threshold voltage of the first flag memory cell corresponds to the third level and a threshold voltage of the second flag memory cells corresponds to the first level,

the read operation under the third condition is performed when the threshold voltage of the second flag memory cell corresponds to the fourth level and a threshold voltage of the third flag memory cells corresponds to the first level, and

the read operation under the fourth condition is performed when the threshold voltage of the third flag memory cell corresponds to the fifth level.