Memory device

1. A memory device, comprising:

a substrate;

an active layer spaced apart from a surface of the substrate and laterally oriented in a first direction, and including a first side, a second side, and a channel layer between the first side and the second side; and

a word line laterally oriented in a second direction crossing the first direction while surrounding the channel layer,

wherein the active layer is configured as a laterally oriented cylinder shape with an inner gap.

2. The memory device of claim 1 , further comprising:

a bit line coupled to the first side of the active layer and vertically oriented with respect to the substrate; and

a capacitor coupled to the second side of the active layer.

3. The memory device of claim 1 , further comprising a gap-fill material filling the inner gap.

4. The memory device of claim 3 , wherein the active layer includes:

a first source/drain region surrounding an end of one side of the gap-fill material; and

a second source/drain region surrounding an end of another end of the gap-fill material.

5. The memory device of claim 1 , wherein the active layer includes a silicon layer, InGaZnO x , InSnZnO x , ZnSnO x , MoS 2 , WS 2 or MoSe 2 .

6. The memory device of claim 1 , wherein the word line includes:

a surrounding portion surrounding the channel layer; and

extended portions extending in the second direction from both sides of the surrounding portion.

7. The memory device of claim 1 , wherein the word line includes:

an upper level portion positioned at a higher level than the channel layer;

a lower level portion positioned at a lower level than the channel layer; and

an intermediate level connection positioned between the upper level portion and the lower level portion while being positioned at the same level as the channel layer.

8. A memory device, comprising:

a plurality of cylindrical active layers including channel layers that are laterally spaced apart from a substrate in a first direction;

a word line extending in a second direction while surrounding the channel layers of the cylindrical active layers;

a bit line coupled to one side of the active layer and vertically oriented in a third direction from the substrate; and

a capacitor coupled to another side of the active layer,

wherein the word line includes:

an upper level portion positioned at a higher level than the channel layers;

a lower level portion positioned at a lower level than the channel layers; and

an intermediate level connection positioned between the upper level portion and the lower level portion while being positioned at the same level as the channel layers, and

wherein each of the cylindrical active layers includes:

an inner gap;

a gap-fill material filling the inner gap;

a first source/drain region surrounding an end of one side of the gap-fill material; and

a second source/drain region surrounding an end of another side of the gap-fill material,

wherein the channel layer includes a plurality of outer sides surrounding the gap-fill material.

9. The memory device of claim 8 , wherein the gap-fill material includes a dielectric material.

10. The memory device of claim 8 , wherein each of the cylindrical active layers is laterally oriented in the second direction crossing the first direction.

11. The memory device of claim 8 , wherein the active layer includes a silicon layer, InGaZnO x , InSnZnO x , ZnSnO x , MoS 2 , WS 2 or MoSe 2 .

12. A memory device, comprising:

a substrate including a peripheral circuit portion;

an active layer including a nano-wire channel spaced apart from the substrate and laterally oriented;

a word line laterally oriented in a direction crossing the nano-wire channel while surrounding the nano-wire channel;

a bit line coupled to an end of one side of the active layer and vertically oriented from the peripheral circuit portion; and

a lateral capacitor coupled to another end of the active layer and spaced apart from the substrate,

wherein the active layer includes:

an inner gap; and

a gap-fill material filling the inner gap,

wherein the inner gap is defined inside the nano-wire channel.

13. The memory device of claim 12 , wherein the active layer further includes a first source/drain region and a second source/drain region between the nano-wire channels, and

wherein the first and second source/drain regions surround the gap-fill material.

14. The memory device of claim 12 , wherein the gap-fill material includes a dielectric material.

15. The memory device of claim 12 , wherein the active layer includes a polysilicon nano-wire, an oxide semiconductor nano-wire, or a compound nano-wire of a transition metal and chalcogen.