Memory device protection

1. An apparatus, comprising:

a group of memory devices; and

a controller coupled to the group of memory devices, the controller configured to:

perform, using first error correction code (ECC) data stored in a first portion of the group of memory devices, an error detection operation on the first portion for indication of a quantity of errors exceeding a threshold quantity within the first portion;

perform an error correction operation on the first portion using at least second ECC data responsive to the indication of the quantity of errors within the first portion exceeding the threshold quantity and that are uncorrectable using third ECC data stored in the first portion of the group of memory devices, wherein the second ECC data is stored in a second portion of the group of memory devices that is coupled to a different channel than a channel to which the first portion of the group of memory devices is coupled; and

perform an error correction operation using the third ECC data to correct the quantity of errors not exceeding the threshold quantity within the first portion without a read operation on the second portion of the group of memory devices to retrieve the second ECC data;

wherein the controller is further configured to swap operational roles of the first portion and the second portion of the group of memory devices to store the second ECC data in the first portion of the group of memory devices.

2. The apparatus of claim 1 , wherein the first ECC data and host data are stored in a same bank of the first portion of the group of memory devices.

3. The apparatus of claim 2 , wherein:

the controller is coupled to the first portion of the group of memory devices via a plurality of pins including a data mask (DM) pin; and

the controller is configured to:

receive the host data via a first portion of the plurality of pins; and

receive, in parallel with the data, the first ECC data via a second portion of the plurality of pins including the DM pin.

4. The apparatus of claim 1 , wherein host data are stored in a first bank and the first ECC data is stored in a second bank.

5. The apparatus of claim 4 , wherein the controller is configured to:

receive the host data from the first bank of the first portion of the group of memory devices; and

perform, using the third ECC stored in the first bank, an error correction operation to correct a quantity of errors not exceeding the threshold quantity on the host data.

6. The apparatus of claim 4 , further comprising a cache coupled to the controller, and wherein the controller is configured to receive, in response to the cache configured for storing the first ECC data, the first ECC data from the cache without receiving the first ECC data from the second bank.

7. The apparatus of claim 1 , wherein the second ECC data comprises parity bits.

8. The apparatus of claim 1 , wherein at least one memory device of the group of memory devices comprises a ferroelectric storage device.

9. An apparatus, comprising:

a plurality of channels, each one of the plurality of channels comprising a respective number of memory devices; and

a controller coupled to the plurality of channels, the controller configured to:

perform an error detection operation on a number of memory devices of a first set of the plurality of channels using first ECC data stored in the first set for indication of a quantity, of errors within one or more memory devices of one channel of the first set exceeding threshold quantity;

in response to the indication of the quantity of errors within the one or more memory devices exceeding the threshold quantity and that are uncorrectable using second ECC data stored in the number of memory devices of the first set, perform an error correction operation to correct the quantity of errors using:

host data stored in a number of memory devices of other channels of the first set; and

third FCC data stored in a number of memory devices of a second set of the plurality of channels; and

perform an error correction operation using second ECC data to correct the quantity of errors not exceeding the threshold quantity without a read operation on the number of memory devices of the second set of the plurality of channels;

wherein the controller is further configured to swap operational roles of the first set and the second set of the plurality of channels to store the host data in the second set of the plurality of channels and the third ECC data in the first set of the plurality of channels.

10. The apparatus of claim 9 , wherein:

at least one of a number of memory devices of a third set of the plurality of channels is a spare device; and

the controller is configured to operate, in response to one memory device of the first set having a quantity of errors exceeding the threshold quantity, the spare device in replacement of the one memory device.

11. The apparatus of claim 9 , wherein the first ECC data comprises a cyclic redundancy check (CRC).

12. The apparatus of claim 9 , wherein the controller is configured to access the plurality of channels in parallel.

13. A system, comprising:

a plurality of groups of memory devices, each one of the plurality of groups of memory devices comprising a respective number of memory devices, wherein:

each one of a number of memory devices of a first portion of the plurality of groups of memory devices configured for storing:

first error correction code (ECC) data to correct a quantity of errors not exceeding a threshold quantity; and

second FCC data for indication of a quantity of errors within data stored in each one of the number of memory devices of the first portion exceeding the threshold quantity; and

a number of memory devices of a second portion of the plurality of groups of memory devices configured for storing third ECC data to correct the quantity of errors within data stored in each one of the number of memory devices of the first portion exceeding the threshold quantity; and

a controller coupled to the plurality of groups of memory devices, the controller configured to:

perform an error correction operation on the number of memory devices of the first portion using the first ECC data to correct the quantity of errors not exceeding the threshold quantity without a read operation on the number of memory devices of the second portion of the plurality of groups of memory devices;

perform an error detection operation on the first portion of the plurality of groups of memory devices using the second ECC data; and

in response to the indication of at least one of the number of memory devices of the first portion having a quantity of errors exceeding the threshold quantity and that are not correctable using the first ECC data, perform an error correction operation on the at least one of the number of memory devices of the first portion using the third ECC data; and

wherein the controller is further configured to swap operational roles of the first portion and the second portion of the group of memory devices to store the third ECC data in the first portion of the group of memory devices.

14. The system of claim 13 , wherein at least one of the number of memory devices of the first portion and at least one of the number of memory devices of the second portion are coupled to a same channel.

15. The system of claim 13 , wherein at least one of a number of memory devices of a third portion is a spare device, and wherein the controller is configured to, in response to one memory device of the first portion having a quantity of errors exceeding the threshold quantity, operate the spare device in replacement of the one memory device of the first portion.

16. The system of claim 13 , wherein the controller is configured to access the plurality of groups of memory devices in parallel.

17. A method, comprising:

performing a read operation on a number of memory devices of a first channel to retrieve:

a first set of host data from a first portion of the number of memory devices of the first channel; and

first ECC data from a second portion of the number of memory devices of the first channel;

performing an error detection operation on the number of memory devices of the first channel using the first ECC data; and

in response to indication, via the error detection operation, of a quantity of errors exceeding a threshold quantity within at least one of the number of memory devices of the first channel and that are not correctable using second ECC data stored in the first portion of the number of memory devices:

performing a read operation on:

a number of memory devices of a second channel to retrieve a second set of host data; and

a number of memory devices of a third channel to retrieve third ECC data that are generated based on the first set of host data and the second set of host data; and

performing, using the third ECC data and the second set of host data, an error correction operation on the number of memory devices of the first channel to correct the quantity of errors exceeding the threshold quantity;

performing an error correction operation using the second ECC data to correct a quantity of errors not exceeding the threshold quantity without performing a read operation on the number of memory devices of the second channel to retrieve the second set of host data or the number of memory devices of the third channel to retrieve the third ECC data; and

swapping operational roles of the first channel and the second channel to store the first set of host data in the number of memory devices of the third channel and the third ECC data in the number of memory devices of the first channel.

18. The method of claim 17 , further comprising:

receiving a write request to write a third set of host data on the number of memory devices of the first channel;

generating fourth ECC data based at least in part on the third set of host data; and

performing a read-modify-write operation to:

write the third set of host data on the number of memory devices of the first channel; and

write the fourth ECC data on the number of memory devices of the third channel.