Detecting timing violations in emulation using field programmable gate array (FPGA) reprogramming

1. A method of detecting a timing violation between a first sequential element and a second sequential element in a circuit design being emulated in a hardware emulation system, the method comprising:

determining a timing relationship between first and second clocks applied respectively to the first sequential element and the second sequential element;

reconfiguring a combinational logic disposed between the first sequential element and the second sequential element as one or more buffers;

setting a delay across the one or more buffers to one or more clock cycles of the hardware emulation system based on the timing relationship;

reprogramming the first and second clocks in accordance with the delay; and

detecting a timing violation if a change in an output of the first sequential element is not stored in the second sequential element based on the reprogrammed first and second clocks.

2. The method of claim 1 further comprising:

setting the delay across the one or more buffers to one cycle of the hardware emulation system clock if the first and second clocks are not synchronous with respect to one another and each of the first and second clocks has a period of at least one emulation clock period; and

setting the delay across the one or more buffers to two cycles of the hardware emulation system clock if the first and second clocks are synchronous with respect to one another.

3. The method of claim 2 further comprising:

setting the delay across the one or more buffers to one cycle of the hardware emulation system clock if the first and second clocks are independent clocks; and

setting the delay across the one or more buffers to two cycles of the hardware emulation system clock if the first and second clocks are a same clock.

4. The method of claim 3 further comprising:

setting the delay across the one or more buffers to N cycles of the hardware emulation system clock, wherein N is a period of the first clock and the second clock defined in terms of a number cycles of the hardware emulation system clock, wherein N is an integer greater than one, wherein the first and second clocks are synchronous with respect to one another.

5. The method of claim 4 further comprising:

reprogramming both the first clock and the second clock so that both the first clock and the second clock have a period defined by the delay.

6. The method of claim 5 further comprising:

reprogramming both the first clock and the second clock so that both the first clock and the second clock have a same pattern with low phases defined by K cycles of the hardware emulation system clock and high phases defined by (M-K) cycles of the hardware emulation system clock if the delay is set to M cycles of the hardware emulation system clock, wherein M is an integer greater than one, and K is a positive integer smaller than M.

7. The method of claim 6 further comprising:

setting output values of the first and second sequential elements using a write-back operation; and

reading the output value of the second sequential element using a read-back operation.

8. The method of claim 7 further comprising:

reconfiguring a first look-up table disposed between the first and second sequential elements as one or more buffers.

9. The method of claim 8 further comprising:

reconfiguring a second look-up table connected to a data input terminal of the first sequential element as either a logic 1 or a logic 0.

10. The method of claim 8 further comprising:

inserting a buffer between a second look-up table and the first sequential element if the second look-up table is configured to supply data to a data input terminal of the first sequential element and to receive data from the combinational logic.

11. The method of claim 1 wherein said hardware emulation system comprises a plurality of field-programmable gate arrays (FPGA).

12. The method of claim 11 wherein the first sequential element is disposed in a first one of the plurality of FPGAs and wherein the second sequential element is disposed in a second one of the plurality of FPGAs.

13. A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:

determine a timing relationship between first and second clocks applied respectively to the first sequential element and the second sequential element;

reconfigure a combinational logic disposed between the first sequential element and the second sequential element as one or more buffers;

set a delay across the one or more buffers to one or more clock cycles of the hardware emulation system based on the timing relationship;

reprogram the first and second clocks in accordance with the delay; and

detect a timing violation if a change in an output of the first sequential element is not stored in the second sequential element based on the reprogrammed first and second clocks.

14. The non-transitory computer readable medium of claim 13 wherein said instructions further cause the processor to:

set the delay across the one or more buffers to one cycle of the hardware emulation system clock if the first and second clocks are not synchronous with respect to one another and each of the first and second clocks has a period of at least one emulation clock period; and

set the delay across the one or more buffers to two cycles of the hardware emulation system clock if the first and second clocks are synchronous with respect to one another.

15. The non-transitory computer readable medium of claim 14 wherein said instructions further cause the processor to:

set the delay across the one or more buffers to one cycle of the hardware emulation system clock if the first and second clocks are independent clocks; and

set the delay across the one or more buffers to two cycles of the hardware emulation system clock if the first and second clocks are a same clock.

16. The non-transitory computer readable medium of claim 15 wherein said instructions further cause the processor to:

set the delay across the one or more buffers to N cycles of the hardware emulation system clock, wherein N is a period of the first clock and the second clock defined in terms of a number cycles of the hardware emulation system clock, wherein N is an integer greater than one, wherein the first and second clocks are synchronous with respect to one another.

17. The non-transitory computer readable medium of claim 16 wherein said instructions further cause the processor to:

reprogram both the first clock and the second clock so that both the first clock and the second clock have a period defined by the delay.

18. The non-transitory computer readable medium of claim 17 wherein said instructions further cause the processor to:

reprogram both the first clock and the second clock so that both the first clock and the second clock have a same pattern with low phases defined by K cycles of the hardware emulation system clock and high phases defined by (M-K) cycles of the hardware emulation system if the delay is set to M cycles of the hardware emulation system clock, wherein M is an integer greater than one, and K is a positive integer smaller than M.

19. The non-transitory computer readable medium of claim 18 wherein said instructions further cause the processor to:

reconfigure a first look-up table disposed between the first and second sequential elements as one or more buffers.

20. The non-transitory computer readable medium of claim 19 wherein said instructions further cause the processor to:

reconfigure a second look-up table connected to a data input terminal of the first sequential element as either a logic 1 or a logic 0.