Method for reducing mismatch of semiconductor element patterns
The invention provides a method for reducing mismatch of semiconductor device patterns, which comprises the following steps: defining an initial lithography area which partially overlaps a target gate structure, a first gate structure and a second gate structure; if a length and a width of the target gate structure are smaller than a preset channel length and a preset channel width respectively, adjusting and reducing the area of the initial lithography area to define a second lithography area. The second lithography area partially overlaps with the target gate structure but does not overlap with the first gate structure and the second gate structure, and the second lithography region is defined as the active area.
1. A method for reducing mismatch of semiconductor device patterns, comprising:
providing a substrate on which a plurality of mutually parallel gate structures are formed, wherein the plurality of gate structures at least comprise a target gate structure, and a first gate structure and a second gate structure which are respectively positioned at two sides of the target gate structure, wherein a channel length of the target gate structure is between 0.1 μm and 0.5 μm, and a channel width of the target gate structure is between 0.5 μm and 3 μm;
defining an active area in a computer system, wherein the method for defining the active area comprises the following steps:
defining an initial lithography area partially overlapping the target gate structure, the first gate structure and the second gate structure;
after the initial lithography area is defined, adjusting and reducing the area of the initial lithography area to define a second lithography area, wherein the second lithography area partially overlaps with the target gate structure but does not overlap with the first gate structure and the second gate structure, and the second lithography area is defined as the active area; and
performing an etching step to transfer the pattern of the active area into the substrate to form a groove in the substrate.
2. The method according to claim 1 , further comprising forming an epitaxial layer in the groove after the groove is formed.
3. The method according to claim 2 , wherein the epitaxial layer does not contact the first gate structure and the second gate structure.
4. The method according to claim 2 , wherein the epitaxial layer is made of SiGe.
5. The method according to claim 1 , wherein there is no other gate structure included between the first gate structure and the target gate structure, and no other gate structure is included between the second gate structure and the target gate structure.