Backside power distribution network semiconductor package and method of manufacturing the same
Provided is a semiconductor architecture including a carrier substrate, a landing pad included in the carrier substrate, a first semiconductor device provided on a first surface of the carrier substrate, the first semiconductor device including a first component provided on the landing pad, and a second semiconductor device provided on a second surface of the carrier substrate, a second component protruding from the second semiconductor device being provided on the landing pad.
1. A semiconductor architecture comprising:
a substrate;
a landing pad included in the substrate;
a first semiconductor device provided on a first surface of the substrate, the first semiconductor device comprising a first component provided on the landing pad; and
a second semiconductor device provided on a second surface of the substrate, a second component protruding from the second semiconductor device being provided on the landing pad,
wherein a width of a horizontal portion of a top surface of the landing pad contacting a bottom surface of the first component is greater than a width of the bottom surface the first component, and
wherein a width of a horizontal portion of a bottom surface of the landing pad contacting a top surface of the second component is greater than a width of the top surface of the second component.
2. The semiconductor architecture according to claim 1 , wherein the landing pad comprises a metal material.
3. The semiconductor architecture according to claim 2 , wherein the metal material comprises one of copper, cobalt, and ruthenium.
4. The semiconductor architecture according to claim 2 , wherein the first component is a buried power rail (BPR) and the second component is a through-silicon via (TSV), and
wherein the landing pad is provided between the BPR and the TSV.
5. The semiconductor architecture according to claim 4 , wherein the BPR and the TSV are in contact with the landing pad.
6. The semiconductor architecture according to claim 4 , further comprising:
a TSV etch stop layer provided between the landing pad and the TSV; and
an encapsulant provided between the landing pad and the BPR,
wherein side surfaces of the TSV etch stop layer and the encapsulation layer are enclosed in the substrate.
7. The semiconductor architecture according to claim 4 , wherein a width of the landing pad is greater than a width of the BPR, and
wherein the width of the landing pad is greater than a width of the TSV.
8. The semiconductor architecture according to claim 1 , wherein the landing pad has a rectangular cross-sectional shape.
9. A semiconductor architecture comprising:
a wafer;
a landing pad provided in the wafer;
a semiconductor device for signal routing provided on a first surface of the wafer, the semiconductor device comprising a BPR provided on the landing pad; and
a power distribution network (PDN) semiconductor device provided on a second surface of the wafer, a TSV protruding from the PDN semiconductor device being provided on the landing pad,
wherein a width of a horizontal portion of a top surface of the landing pad contacting a bottom surface of the BPR is greater than a width of the bottom surface the BPR, and
wherein a width of a horizontal portion of a bottom surface of the landing pad contacting a top surface of the TSV is greater than a width of the top surface of the TSV.