Semiconductor memory device including a plurality of memory blocks and method of manufacturing the same
A semiconductor memory device may include a plurality of memory blocks and at least one insulation bridge. The plurality of the memory blocks may be defined by a plurality of slits parallel to each other. The at least one insulation bridge may be formed in at least one slit located on at least one side of a memory block of the plurality of memory blocks to support the adjacent memory blocks.
1. A semiconductor memory device comprising:
a plurality of memory blocks divided by a plurality of slits, each of the memory blocks including a plurality of conductive layers sequentially stacked and a plurality of insulation layers interposed between the plurality of conductive layers; and
at least one insulation bridge formed in each of the slits,
wherein the insulation bridge includes a plurality of insulation layers extended from the plurality of insulation layers of adjacent memory blocks, and at least one space positioned between the plurality of insulation layers constituting the bridge, respectively.
2. The semiconductor memory device of claim 1 , wherein each of the memory blocks comprises:
at least one channel structure formed in the stacked structure.
3. The semiconductor memory device of claim 1 , wherein the at least one insulation bridge of each of the slits is arranged to face each other.
4. The semiconductor memory device of claim 1 , wherein the at least one insulation bridge of each of the slits is arranged to be non-corresponding each other.
5. The semiconductor memory device of claim 1 , wherein numbers of the insulation bridge formed in each slit correspond to each other.
6. The semiconductor memory device of claim 1 , wherein numbers of the insulation bridges formed in each slit are different.
7. A semiconductor memory device comprising:
a plurality of memory blocks including a plurality of insulation layers and a plurality of conductive layers which are alternately stacked from a bottom portion of each of the plurality of memory blocks toward an upper portion of each of the plurality of memory blocks; and
at least one bridge located in each of slits positioned between the plurality of memory blocks,
wherein the bridge includes a plurality of insulation layers stacked from the bottom portion to the upper portion, and
at least one space is positioned between the plurality of insulation layers constituting the bridge, respectively.
8. The semiconductor memory device of claim 7 , wherein the plurality of insulation layers of the bridge are extended from the plurality of insulation layers of adjacent memory blocks, respectively.
9. The semiconductor memory device of claim 7 , wherein the at least one bridge includes a plurality of bridges spaced apart from each other.
10. The semiconductor memory device of claim 9 , wherein the plurality of bridges of each of the slits are arranged to be non-corresponding to each other.
11. A semiconductor memory device comprising:
a first stacked structure including a plurality of conductive layers stacked from a first level toward a second level higher than the first level and a plurality of insulation layers interposed between the plurality of conductive layers;
a second stacked structure spaced apart from the first stacked structure by a first slit, the second stacked structure including a plurality of conductive layers stacked from the first level toward the second level and a plurality of insulation layers interposed between the plurality of conductive layers constituting the second stacked structure; and
a plurality of first bridges arranged to be spaced apart from each other in the first slit, each of the first bridges including a plurality of insulation layers which connect to the plurality of insulation layers of the first stacked structure and the plurality of insulation layers of the second stacked structure, respectively; and
at least one space positioned between the plurality of insulation layers constituting each of the first bridges, respectively.
12. The semiconductor memory device of claim 11 , further comprising:
a third stacked structure spaced apart from the second stacked structure by a second slit, the third stacked structure including a plurality of conductive layers stacked from the first level toward the second level and a plurality of insulation layers interposed between the plurality of conductive layers constituting the third stacked structure; and
a plurality of second bridges arranged to be spaced apart from each other in the second slit, each of the second bridges including a plurality of insulation layers which connect to the plurality of insulation layers of the second stacked structure and the plurality of insulation layers of the third stacked structure, respectively.
13. The semiconductor memory device of claim 12 , further comprising at least one space positioned between the plurality of insulation layers constituting each of the second bridges, respectively.
14. The semiconductor memory device of claim 12 , wherein the plurality of first bridges and the plurality of second bridges are arranged to be non-corresponding to each other.