IP Library › Granted Patent US 12,272,610
Granted Patent B2
US 12,272,610 · App. 17/160,462 · Granted Apr 8, 2025

Semiconductor package with stiffener

Inventor: Hansung Ryu (Seoul, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L23/053H01L23/3672H01L23/562H01L25/0655
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Quick Facts
Patent No.
US 12,272,610
App. No.
17/160,462
Granted
Apr 8, 2025
Kind
B2
Abstract

A semiconductor package includes a substrate, a semiconductor stack mounted on the substrate, and a stiffener surrounding the semiconductor stack, the stiffener having an octagonal shape at an edge of an upper surface thereof. A minimum distance from one angular point of an upper surface of the substrate to the stiffener is determined based on the thickness of the substrate.

Claims (61)

1. A semiconductor package comprising:

a substrate having

first sides opposing each other,

and second sides opposing each other and intersecting the first sides;

a semiconductor stack mounted on the substrate, wherein the semiconductor stack defines a stack area having first edges parallel to the first sides and second edges parallel to the second sides; and

a stiffener including a plurality of frames surrounding the stack area on the substrate, wherein the plurality of the frames of the stiffener includes

first frames disposed adjacent the first sides of the substrate, spaced a first distance from the first edges of the stack area, and surrounding at least a portion of the first edges,

second frames disposed adjacent the second sides of the substrate, spaced a second distance from the second edges of the stack area, and surrounding at least a portion of the second edges, and

third frames connecting the first frames and the second frames to each other,

wherein, in plan view, the plurality of the frames of the stiffener have an octagonal shape,

wherein the first frames are spaced apart from the first sides of the substrate or the second frames are spaced apart from the second sides of the substrate, and

wherein a closest distance from (i) an intersection point between the first sides and the second sides at an outer corner of the substrate and at an upper surface of the substrate to (ii) an outer side of the third frames of the stiffener is at least 3.5 times a thickness of the substrate, wherein the thickness of the substrate is measured in a vertical direction perpendicular to the upper surface of the substrate,

wherein a width of the plurality of the frames of the stiffener is at least 20% the thickness of the substrate and less than the thickness of the substrate, wherein the width of the plurality of the frames is measured in a lateral direction parallel to the upper surface of the substrate, and

wherein the intersection point is laterally outside the plurality of frames.

2. The semiconductor package according to claim 1 , wherein the closest distance is 10.5 times the thickness of the substrate.

3. The semiconductor package according to claim 1 , wherein the first frames are aligned with the first sides of the substrate.

4. The semiconductor package according to claim 1 , wherein a stiffness of the stiffener is equal to or more than a stiffness of the substrate.

5. The semiconductor package according to claim 1 , wherein the stiffener has a height equal to 100% to 200% of the thickness of the substrate.

6. The semiconductor package according to claim 1 , wherein an outer side wall of the first frames of the stiffener is spaced apart from the first sides of the substrate by a third distance less than the first distance, and an outer side wall of the second frames of the stiffener is spaced apart from the second sides of the substrate by a fourth distance less than the second distance when viewed in a top view.

7. The semiconductor package according to claim 1 , wherein the closest distance is a length of a line extending from the intersection point to the outer side of the third frames of the stiffener, wherein the line is perpendicular to the outer side of the third frames of the stiffener.

8. The semiconductor package according to claim 1 , further comprising:

a first thermal transfer material provided between the substrate and the stiffener.

9. The semiconductor package according to claim 1 , further comprising:

a heat dissipation plate provided on the stiffener, the heat dissipation plate covering the semiconductor stack.

10. A semiconductor package comprising:

a substrate having

first sides opposing each other, and

second sides opposing each other and intersecting the first sides;

a semiconductor stack mounted on the substrate, wherein the semiconductor stack defines a stack area having first edges parallel to the first sides and second edges parallel to the second sides; and

a stiffener including a plurality of frames surrounding the stack area on the substrate,

wherein a closest distance from (i) an intersection point between the first sides and the second sides at an outer corner of the substrate and at an upper surface of the substrate to (ii) an outer side of the stiffener is greater than a width of the plurality of the frames of the stiffener,

wherein the closest distance is at least 3.5 times a thickness of the substrate, wherein the thickness of the substrate is measured in a vertical direction perpendicular to the upper surface of the substrate,

wherein the width of the plurality of the frames of the stiffener is at least 20% the thickness of the substrate and less than the thickness of the substrate, wherein the width of the plurality of the frames is measured in a lateral direction parallel to the upper surface of the substrate, and

wherein the intersection point is laterally outside the plurality of frames.

11. The semiconductor package according to claim 10 , wherein a shape formed by the plurality of frames comprises, in plan view, any one of a hexagonal shape, a decagonal shape, and a dodecagonal shape.

12. The semiconductor package according to claim 10 ,

wherein the plurality of the frames of the stiffener comprises:

first frames extending along the first sides of the substrate, spaced apart from the first edges of the stack area, and surrounding at least a portion of the first edges;

third frames extending along second sides of the substrate, spaced apart from the second edges of the stack area, and surrounding at least a portion of the second edges; and

second frames connecting the first frames and the third frames to each other, and

wherein each of the second frames has a shape convex with respect to the intersection point.

13. The semiconductor package according to claim 10 , wherein the plurality of the frames of the stiffener are spaced apart from the first sides and the second sides of the substrate when viewed in a top view.

14. The semiconductor package according to claim 10 , wherein the closest distance is a length of a line extending from the intersection point to an outer side of frames located adjacent to the intersection point among the plurality of the frames of the stiffener, wherein the line is perpendicular to the outer side of the frames.

15. A semiconductor package comprising:

a substrate having

first sides opposing each other, and

second sides opposing each other and intersecting the first sides;

a semiconductor stack mounted on the substrate, wherein the semiconductor stack defines a stack area having first edges parallel to the first sides and second edges parallel to the second sides;

a stiffener including a plurality of frames spaced apart from the first sides and the second sides of the substrate and surrounding the stack area on the substrate;

a first thermal transfer material provided between the substrate and the stiffener;

a heat dissipation plate provided on the stiffener, the heat dissipation plate covering the semiconductor stack;

a second thermal transfer material provided between the stiffener and the heat dissipation plate;

a heat sink provided on the heat dissipation plate; and

a third thermal transfer material provided between the heat dissipation plate and the heat sink,

wherein a closest distance from (i) an intersection point between the first sides and the second sides at an outer corner of the substrate and at an upper surface of the substrate to (ii) an outer side of the stiffener is greater than a width of the plurality of the frames of the stiffener,

wherein the closest distance is at least 3.5 times a thickness of the substrate, wherein the thickness of the substrate is measured in a vertical direction perpendicular to the upper surface of the substrate,

wherein the width of the plurality of the frames of the stiffener is at least 20% the thickness of the substrate and less than the thickness of the substrate, wherein the width of the plurality of the frames is measured in a lateral direction parallel to the upper surface of the substrate, and

wherein the intersection point is laterally outside the plurality of frames.

16. The semiconductor package according to claim 15 , wherein a shape formed by the plurality of frames comprises an octagonal shape.

17. The semiconductor package according to claim 15 , wherein the closest distance is a length of a line extending from the intersection point to an outer side of frames located adjacent to intersection point among the plurality of the frames of the stiffener, wherein the line is perpendicular to the outer side of the frames.

18. The semiconductor package according to claim 15 , wherein a height of the plurality of the frames of the stiffener is 100% to 200% of the thickness of the substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2021
From: RYU, HANSUNG
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 055349/0424 →
Priority Claims (1)
KR 10-2020-0103278 · Aug 18, 2020 · national
Continuity (1)
Related Publication 20220059420A1 · Feb 24, 2022
References Cited (20)
US 5566448A · Bhatt · 1996 [cited by examiner]
US 7102228B2 · Kanda · 2006 [cited by applicant]
US 7352062B2 · Joshi et al. · 2008 [cited by applicant]
US 8014154B2 · Lee · 2011 [cited by applicant]
US 8217500B1 · Hool · 2012 [cited by examiner]
US 8642445B2 · Chen et al. · 2014 [cited by applicant]
US 9867282B2 · Hu et al. · 2018 [cited by applicant]
US 10468318B2 · Ahmad et al. · 2019 [cited by applicant]
US 10629545B2 · Huang et al. · 2020 [cited by applicant]
US 20030000736A1 · Sathe · 2003 [cited by examiner]
US 20030230800A1 · Akai · 2003 [cited by examiner]
US 20050062143A1 · Joshi · 2005 [cited by examiner]
US 20100276799A1 · Heng · 2010 [cited by examiner]
US 20120182694A1 · Lin · 2012 [cited by examiner]
US 20150049441A1 · Hu · 2015 [cited by examiner]
US 20180233459A1 · Fushimi · 2018 [cited by applicant]
US 20180261528A1 · Chen · 2018 [cited by examiner]
US 20190006294A1 · Ong · 2019 [cited by examiner]
US 20190237371A1 · Ahmad · 2019 [cited by examiner]
US 20210225729A1 · Bozorg-Grayeli · 2021 [cited by examiner]