Advanced seal ring structure and method of making the same
View Patent ↗A semiconductor structure includes a substrate having a seal ring region and a circuit region; one or more dielectric layers disposed on the substrate; a connection structure disposed in the one or more dielectric layers in the seal ring region, wherein the connection structure includes a stack of metal layers and metal vias connecting the stack of metal layers; and a metal plug disposed between the substrate and the connection structure in the seal ring region, wherein the metal plug has a multi-step profile in a cross-sectional view.
1. A semiconductor structure, comprising:
a substrate having a seal ring region and a circuit region;
one or more dielectric layers disposed on the substrate;
a connection structure disposed in the one or more dielectric layers in the seal ring region, wherein the connection structure includes a stack of metal layers and metal vias connecting the stack of metal layers; and
a metal plug disposed between the substrate and the connection structure in the seal ring region, wherein the metal plug has a multi-step profile in a cross-sectional view.
2. The semiconductor structure of claim 1 , wherein the metal plug includes a ring structure surrounding the circuit region from a top view.
3. The semiconductor structure of claim 1 , wherein the metal plug includes multiple segments that surround the circuit region from a top view.
4. The semiconductor structure of claim 1 , further comprising:
a via bar disposed on the metal plug and connecting the metal plug to the connection structure.
5. The semiconductor structure of claim 1 , further comprising:
multiple vias disposed on the metal plug and connecting the metal plug to the connection structure.
6. The semiconductor structure of claim 1 , further comprising:
a gate structure adjacent to the metal plug and disposed between the substrate and the connection structure in the seal ring region.
7. The semiconductor structure of claim 6 , further comprising:
a via bar disposed on the gate structure and connecting the gate structure to the connection structure.
8. The semiconductor structure of claim 1 , wherein the metal plug includes a conductive adhesion promoter in direct contact with a first dielectric layer on sidewalls of the metal plug, wherein a top portion of the metal plug extends higher than the conductive adhesion promoter.
9. The semiconductor structure of claim 1 , further comprising:
a silicide layer between the substrate and the metal plug, wherein the metal plug is disposed on the silicide layer.
10. The semiconductor structure of claim 1 , wherein the substrate further includes an assembly isolation region between the seal ring region and the circuit region, further comprising:
dummy vias disposed in the one or more dielectric layers in the assembly isolation region; and
a second metal plug disposed between the substrate and the dummy vias in the assembly isolation region.
11. The semiconductor structure of claim 10 , wherein the second metal plug is isolated from the dummy vias.
12. A semiconductor structure, comprising:
a substrate having a seal ring region surrounding a circuit region;
dielectric layers disposed on the substrate;
a connection structure disposed in the dielectric layers in the seal ring region, wherein the connection structure includes metal layers in a stacking configuration;
first metal plugs disposed between the substrate and the connection structure in the seal ring region, wherein each of the first metal plugs includes a cobalt core and a conductive barrier layer surrounding the cobalt core, wherein the cobalt core has at least two steps in a cross-sectional view; and
first metal vias disposed on the first metal plugs and connecting the first metal plugs to the connection structure.
13. The semiconductor structure of claim 12 , wherein at least one of the first metal plugs includes a ring structure that surrounds the circuit region from a top view.
14. The semiconductor structure of claim 12 , further comprising first gate structures between the substrate and the connection structure in the seal ring region, wherein the first metal plugs and the first gate structures are disposed in an alternating manner.
15. The semiconductor structure of claim 14 , wherein the substrate further has an assembly isolation region between the seal ring region and the circuit region, further comprising second metal plugs and second gate structures over the substrate in the assembly isolation region.
16. The semiconductor structure of claim 12 , wherein at least one of the first metal vias is configured as a ring structure surrounding the circuit region.
17. A semiconductor structure, comprising:
a substrate having a first seal ring region and a second seal ring region surrounding a circuit region;
dielectric layers disposed on the substrate; and
multiple seal rings configured in each of the first and the second seal ring regions, wherein each of the seal rings includes:
a connection structure disposed in the dielectric layers and having a stack of interconnected metal layers,
a metal plug disposed between the substrate and the connection structure, wherein the metal plug includes a metal core that has at least three sections and the three sections become wider as they are further away from the substrate, and
a metal via disposed on the metal plug and connecting the metal plug to the connection structure.
18. The semiconductor structure of claim 17 , wherein the metal plug includes a conductive adhesion promoter between the metal core and a first dielectric layer surrounding the metal plug, wherein a topmost section of the three sections is above the conductive adhesion promoter.
19. The semiconductor structure of claim 17 , wherein the metal core includes cobalt.
20. The semiconductor structure of claim 17 , wherein the metal plug is configured as a ring structure surrounding the circuit region.