Level shifter with reduced duty cycle variation
Disclosed are level shifters and methods of performing level shifting. In one embodiment, a level shifter is disclosed comprising an input, cross-coupled/latch circuitry, a first reference node, a second reference node, and output circuitry coupled between the cross-coupled/latch circuitry and an output, wherein the output circuitry sets the output signal to high based on rising edge of a second reference node and sets the output signal to low based on the rising edge of the first reference node. Further, in some implementations, the first reference node and the second reference node may have signals that are inverse to each other.
1. A level shifter device comprising:
an input node coupled to an input of the level shifter device;
cross-coupled latch circuitry coupled to the input node and including a first transistor and a second transistor that are cross-coupled;
a first reference node connected to a gate of the first transistor;
a second reference node connected to the gate of the second transistor;
a first inverter circuit with the first reference node as an input and a third reference node as an output; and
output circuitry coupled to an output of the level shifter device, the output circuitry having a first PMOS transistor with a source coupled to a high supply voltage, a drain coupled to the output of the level shifter device and a gate connected to the third reference node, and the output circuitry having a first NMOS transistor with a source coupled to a low supply voltage, a drain coupled to the output of the level shifter device and a gate connected to the second reference node.
2. The device of claim 1 , wherein a rise of voltage at the output of the level shifter device is triggered as a function of a rising edge of the first reference node.
3. The device of claim 1 , further comprising input circuitry coupled between the input node and the first and second reference node.
4. The device of claim 3 , wherein the input circuitry includes a second inverter circuit.
5. The device of claim 3 , further comprising an enable circuit coupled between the input circuitry and the first reference node to enable a voltage level at the first reference node to change in response to a voltage change at the input node.
6. The device of claim 5 , wherein the enable circuit is controlled by an enable signal.
7. The device of claim 6 , wherein the enable signal is coupled to the first inverter circuit for enabling the first inverter circuit.
8. The device of claim 6 , further comprising a second PMOS transistor having a source coupled to the high power supply voltage, a drain coupled to the first reference node and a gate coupled to the enable signal for enabling a voltage at the first reference node to change in response to a voltage change at the input node.
9. The device of claim 6 , wherein the enable circuit includes a first enable transistor coupled between the first reference node and the input circuitry and a second enable transistor coupled between the second reference node and the input circuitry, a gate of the first enable transistor and a gate of the second enable transistor being coupled to the enable signal to enable voltages at the first reference node and the second reference node to change in response to a voltage change at the input node.
10. The device of claim 3 , wherein the cross-coupled latch circuitry further includes a third transistor coupled between the first transistor and the input circuitry and a fourth transistor coupled between the second transistor and the input circuitry.
11. The device of claim 1 wherein the output is set to high based on the rising edge of a signal on the first reference node at a 4-gate delay from the input, and the output is set to low based on the rising edge of a signal on the second reference node at a 4-gate delay from the input.
12. The device of claim 1 wherein the output is set to high based on the rising edge of a signal on the first reference node at first gate delay from the input, and the output is set to low based on the rising edge of a signal on the second reference node at a second gate delay from the input, wherein the first gate delay is equal to the second gate delay.