Elemental composition tuning for chalcogenide based memory arranged in a plurality of decks
A memory device including a memory array comprising a plurality of decks, a respective deck comprising a plurality of memory cells, a respective memory cell comprising a storage element comprising a chalcogenide material; wherein a first deck of the plurality of decks comprises first memory cells with storage elements deposited at a first initial composition of a plurality of elements; and a second deck of the plurality of decks comprises second memory cells with storage elements deposited at a second initial composition of the plurality of elements.
1 . A memory device including:
a memory array comprising a plurality of decks, a respective deck comprising a plurality of memory cells, a respective memory cell comprising a storage element comprising a chalcogenide material; wherein:
a first deck and a third deck of the plurality of decks comprise first memory cells with storage elements deposited at a first initial composition of a plurality of elements;
a second deck and a fourth deck of the plurality of decks comprise second memory cells with storage elements deposited at a second initial composition of the plurality of elements different from the first initial composition of the plurality of elements; and
wherein the first initial composition and second initial composition are selected such that after a particular number of program cycles have been performed to the first memory cells and the particular number of program cycles have been performed to the second memory cells:
a third altered local composition of the first memory cells more closely matches a fourth altered local composition of the second memory cells than the first initial composition and the second initial composition.
2 . The memory device of claim 1 , wherein the first memory cells with storage elements deposited at the first initial composition are coupled to first access circuitry to program the first memory cells using a first program pulse having a positive polarity and the second memory cells with storage elements deposited at the second initial composition are coupled to second access circuitry to program the second memory cells using a second program pulse having a negative polarity.
3 . The memory device of claim 1 , wherein the first deck and the third deck of the plurality of decks are outer decks and the second deck and fourth deck of the plurality of decks are inner decks.
4 . The memory device of claim 1 , wherein the first initial composition and second initial composition include differing percentages of the plurality of elements.
5 . The memory device of claim 1 , wherein the second deck is between the first deck and the third deck and wherein the third deck is between the second deck and the fourth deck.
6 . The memory device of claim 1 , wherein a fifth deck of the plurality of decks comprises third memory cells with storage elements deposited at a third initial composition of the plurality of elements.
7 . The memory device of claim 1 , wherein respective memory cells of the plurality of decks comprise a first layer of chalcogenide material to function as a selector device and a second layer of chalcogenide material to function as the storage element.
8 . The memory device of claim 1 , further comprising a plurality of memory chips, wherein a first memory chip of the plurality of memory chips comprises the memory array.
9 . The memory device of claim 8 , further comprising a memory controller to communicate with the plurality of memory chips.
10 . The memory device of claim 1 , wherein the memory device comprises a solid state drive or a dual in-line memory module.
11 . A method comprising:
forming a first deck and a third deck of first memory cells, wherein forming the first deck and the third deck comprises depositing a plurality of storage elements of the first memory cells at a first initial composition of a plurality of elements of a chalcogenide material;
forming a second deck and a fourth deck of second memory cells, wherein forming the second deck and the fourth deck of second memory cells comprises depositing a plurality of storage elements of the second memory cells at a second initial composition of the plurality of elements different from the first initial composition of the plurality of elements of the chalcogenide material; and
selecting the first initial composition and second initial composition such that after a particular number of program cycles have been performed to the first memory cells and the particular number of program cycles have been performed to the second memory cells:
a third altered local composition of the first memory cells more closely matches a fourth altered local composition of the second memory cells than the first initial composition and the second initial composition.
12 . The method of claim 11 , further comprising forming, between the first deck and the second deck, a layer of access lines to be shared by the first deck and the second deck.
13 . The method of claim 11 , wherein a difference between the first and second initial compositions is based on a difference in a thermoelectric dynamic environment between the first deck and the second deck.
14 . The method of claim 11 , further comprising forming a fifth deck of third memory cells above the second deck of memory cells, wherein forming the fifth deck of third memory cells comprises depositing a plurality of storage elements of the third memory cells at a third initial composition of the plurality of elements of the chalcogenide material.
15 . The method of claim 11 , wherein the first deck of the plurality of decks is an inner deck and the second deck of the plurality of decks is an outer deck.
16 . The method of claim 11 , wherein the first initial composition and second initial composition include differing percentages of the plurality of elements.
17 . The method of claim 11 , further comprising selecting the first initial composition of the plurality of elements of the chalcogenide material based on geometries of storage elements or surrounding components of the first memory cells, a direction of current flow in the first memory cells during program and read operations, a speed for program and read operations of the first memory cells, an endurance of the first memory cells, an energy usage to perform program and read operations, a distribution width of speeds among the first memory cells, a nucleation speed, and a growth speed.
18 . A system comprising:
a storage device controller; and
at least one memory chip coupled to the storage device controller, wherein a memory chip comprises:
a memory array comprising a plurality of decks, a respective deck comprising a plurality of memory cells, a respective memory cell comprising a storage element comprising a chalcogenide material; wherein:
a first deck and a third deck of the plurality of decks comprise first memory cells with storage elements deposited at a first initial composition of a plurality of elements;
a second deck and a fourth deck of the plurality of decks comprise second memory cells with storage elements deposited at a second initial composition of the plurality of elements different from the first initial composition of the plurality of elements; and
wherein the first initial composition and second initial composition are selected such that after a particular number of program cycles have been performed to the first memory cells and the particular number of program cycles have been performed to the second memory cells:
a third altered local composition of the first memory cells more closely matches a fourth altered local composition of the second memory cells than the first initial composition and the second initial composition.
19 . The system of claim 18 , further comprising a processor to generate data to be stored by the memory array, the processor to couple to the at least one memory chip through the storage device controller.
20 . The system of claim 19 , further comprising one or more of: a battery communicatively coupled to the processor, a display communicatively coupled to the processor, or a network interface communicatively coupled to the processor.