Scan circuit and method

1. A method for detecting faults in an integrated circuit (IC), the method comprising:

entering scan mode of the IC;

receiving, at the IC, a test pattern;

applying, at the IC, the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain;

while applying the test pattern through the first scan chain, controlling, at the IC, a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and

evaluating an output of the first scan chain to detect faults in the IC.

2. The method of claim 1 , wherein the further scan enable input is kept high while applying the test pattern through the first scan chain.

3. The method of claim 1 , further comprising decompressing a compressed input test pattern to generate the test pattern.

4. The method of claim 1 , wherein controlling the further scan flip-flop with the first scan chain comprises controlling the further scan flip-flop with an output of a first given scan flip-flop of the first scan chain, the output of the first given scan flip-flop further coupled to an SI input of a second given scan flip-flop of the first scan chain, the method further comprising:

generating a selection signal; and

selectively connecting the output of the second given scan flip-flop or an output of the further scan flip-flop with an input of a third given scan flip-flop of the first scan chain based on the selection signal.

5. The method of claim 4 , wherein generating the selection signal comprises generating the selection signal based on a register bit.

6. The method of claim 4 , wherein generating the selection signal comprises generating the selection signal based on a scan flip-flop of a further scan chain.

7. The method of claim 6 , wherein the first scan chain is dependent on compression and the further scan chain is not dependent on compression.

8. The method of claim 1 , wherein receiving the test pattern comprises receiving the test pattern from an LBIST controller.

9. The method of claim 1 , wherein receiving the test pattern comprises receiving the test pattern from an automated test equipment (ATE).

10. The method of claim 1 , wherein entering scan mode comprises asserted a scan mode signal.

11. An integrated circuit comprising:

a plurality of logic circuits; and

a scan circuit, wherein the integrated circuit is configured to:

enter scan mode;

receive a test pattern;

apply the test pattern through a first scan chain of the scan circuit by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; and

while applying the test pattern through the first scan chain, controlling a further scan flip-flop of the scan circuit with the first scan chain without transitioning a further scan enable input of the further scan flip-flop.

12. The integrated circuit of claim 11 , further comprising an LBIST controller configured to provide the test pattern.

13. The integrated circuit of claim 11 , further comprising an OR gate having an output coupled the further scan enable input of the further scan flip-flop, the output of the OR gate being indicative of whether the integrated circuit is in scan mode.

14. The integrated circuit of claim 11 , wherein the scan circuit further comprises a multiplexer (MUX) having a first input coupled to an output of a scan flip-flop of the first scan chain, a second input coupled to an output of the further scan flip-flop, and an output coupled to the first scan chain.

15. The integrated circuit of claim 14 , further comprising a second further scan flip-flop having an output coupled to a selection input of the MUX.

16. The integrated circuit of claim 15 , wherein the second further scan flip-flop is part of a second scan chain different form the first scan chain.

17. The integrated circuit of claim 15 , further comprising a third further scan flip-flop having a clock input coupled to a scan enable input of the second further scan flip-flop, and an output coupled to the selection input of the MUX.

18. The integrated circuit of claim 15 , further comprising a latch coupled between the second further scan flip-flop and the selection input of the MUX.

19. A method for detecting faults in an integrated circuit (IC), the method comprising:

entering scan mode of the IC;

receiving, at the IC, a test pattern;

selecting a sub-scan chain to become part of a first scan chain;

applying, at the IC, the test pattern through the first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain;

while applying the test pattern through the first scan chain, controlling, at the IC, an unselected sub-scan chain with the first scan chain without transitioning a scan enable input of a scan flip-flop of the unselected sub-scan chain, wherein the selected sub-scan chain has a length of N, the unselected sub-scan chain has a length of N, and N is a positive integer greater than or equal to 1; and

evaluating an output of the first scan chain to detect faults of the IC.

20. The method of claim 19 , wherein the first scan chain has a length of N.

21. A method comprising:

entering scan mode of an integrated circuit (IC);

receiving, at the IC, test patterns;

decompressing, at the IC, the test patterns;

dynamically selecting, at the IC, scan chains from a plurality of scan chains;

applying, at the IC, the decompressed test patterns to the selected scan chains by pulsing a clock signal and transitioning a scan enable signal coupled to the selected scan chains; and

applying, at the IC, the decompressed test patterns to unselected scan chains without transitioning a scan enable signal coupled to the unselected scan chains;

compressing, at the IC, outputs of the plurality of scan chains; and

evaluating the compressed outputs to detect faults of the IC.