Analog switch multiplexer systems and related methods
A motor controller system that includes an analog switch multiplexer system is disclosed. Specific implementations include a plurality of field effect transistors (FETs) that may be configured to be operatively coupled with one or more phases of a motor. Each of the plurality of FETs may include a gate, an analog switch multiplexer coupled with each of the gates of the plurality of FETs and with an analog output, and a digital control block coupled with the analog switch multiplexer that may be configured to send a multiplexer select control signal to the analog switch multiplexer in response to receiving a serial peripheral interface signal.
1. An analog switch system, comprising:
a first PMOS transistor coupled with a first diode;
a second PMOS transistor coupled with a second diode, the second PMOS transistor and the second diode coupled with the first PMOS transistor and the first diode;
a first NMOS transistor coupled with a third diode; and
a second NMOS transistor coupled with a fourth diode, the second NMOS transistor and the fourth diode coupled with the first NMOS transistor and the third diode;
wherein the first PMOS and second PMOS transistor are coupled with the first NMOS transistor and the second NMOS transistor; and
wherein the system is configured to operate at a voltage up to a drain breakdown voltage of one of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, or the second NMOS transistor.
2. The system of claim 1 , further comprising a second pin coupled to the second PMOS transistor and to the second NMOS transistor.
3. The system of claim 1 , further comprising a third NMOS transistor comprising a gate coupled with a digital control block and with a gate of the first NMOS transistor and a gate of the second NMOS transistor.
4. The system of claim 1 , further comprising a first current source coupled with a fifth diode coupled with a third NMOS transistor, the first current source coupled with a resistor coupled with a fourth NMOS transistor coupled with a sixth diode coupled to a gate control voltage input.
5. The system of claim 4 , further comprising a second current source coupled in parallel with a gate of the fourth NMOS transistor and coupled with the resistor.
6. The system of claim 5 , wherein the gate of the fourth NMOS transistor is coupled between the first PMOS transistor, the second PMOS transistor, and the first diode and the second diode.
7. An analog switch system, comprising:
a first PMOS transistor and a second PMOS transistor coupled with a first diode and with a second diode, respectively, the first diode directed inside and the second diode directed inside; and
a first NMOS transistor and a second NMOS transistor coupled with a third diode and with a fourth diode, respectively, the third diode directed outside and the fourth diode directed outside;
wherein the first PMOS transistor and second PMOS transistor are coupled in parallel with the first NMOS transistor and the second NMOS transistor.
8. The system of claim 7 , further comprising a first pin coupled to the first PMOS transistor and to the second NMOS transistor.
9. The system of claim 7 , wherein the second PMOS transistor and the second diode is coupled in series with the first PMOS transistor and the first diode.
10. The system of claim 7 , further comprising a second pin coupled to the second PMOS transistor and to the second NMOS transistor.
11. The system of claim 7 , wherein the second NMOS transistor and the fourth diode are coupled in series with the first NMOS transistor and the third diode.
12. The system of claim 7 , further comprising a third NMOS transistor comprising a gate coupled with a digital control block and with a gate of the first NMOS transistor and a gate of the second NMOS transistor.
13. The system of claim 7 , further comprising a first current source coupled with a fifth diode coupled with a third NMOS transistor, the first current source coupled with a resistor coupled with a fourth NMOS transistor coupled with a sixth diode coupled to a gate control voltage input.
14. The system of claim 13 , further comprising a second current source coupled in parallel with a gate of the fourth NMOS transistor and coupled with the resistor.
15. The system of claim 14 , wherein the gate of the fourth NMOS transistor is coupled between the first PMOS transistor, the second PMOS transistor, and the first diode and the second diode.
16. A method of operating an analog switch multiplexer circuit, the method comprising:
using a digital control block, applying an ON voltage to a gate of an NMOS transistor coupled with a diode and a current source;
in response to receiving the ON voltage at two NMOS transistors coupled in parallel with the ON voltage, turning on the two NMOS transistors, the two NMOS transistors coupled in parallel with a first PMOS transistor and with a second PMOS transistor;
turning on the first PMOS transistor and the second PMOS transistor; and
while the first PMOS transistor and the second PMOS transistor are on, transmitting an analog gate voltage of a field effect transistor (FET) from a first pin to a second pin through a channel of the first PMOS transistor and a channel of the second PMOS transistor;
wherein the analog gate voltage is a voltage up to a drain breakdown voltage of one of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, or the second NMOS transistor.
17. The method of claim 16 , further comprising using the digital control block, applying an OFF voltage to the gate of the NMOS transistor coupled with the diode and the current source.
18. The method of claim 17 , wherein applying an OFF voltage further comprises:
turning off a current flow from the current source; and
closing the NMOS transistor and turning off each gate of the PMOS transistors.
19. The method of claim 16 , wherein a gate control voltage flows to ground through a fourth NMOS transistor, a resistor, and a first current source.
20. The method of claim 16 , further comprising transmitting the analog gate voltage to one of the first pin or the second pin in response to applying a voltage to one of the second pin or the first pin, respectively.