Semiconductor memory device and manufacturing method of semiconductor memory device

1. A semiconductor memory device comprising:

a peripheral circuit layer;

a bonding structure disposed over the peripheral circuit layer;

a channel structure disposed over the bonding structure;

a first gate contact structure including a first vertical part penetrating the bonding structure and a first horizontal part intersecting with the first vertical part and extending from the first vertical part;

a first gate conductive pattern coupled to a sidewall of the first horizontal part and spaced apart from the first vertical part by a gap,

wherein the first gate conductive pattern extends to surround the channel structure; and

a first gate spacer insulating layer including a first portion having a first width between the first vertical part and the first gate conductive pattern, and a second portion having a second width smaller than the first width on a portion of the first vertical part,

wherein the first portion and the second portion are located at a same level.

2. The semiconductor memory device of claim 1 ,

wherein the bonding structure includes a structure in which dielectric layers are bonded together.

3. The semiconductor memory device of claim 1 , further comprising:

a second gate conductive pattern surrounding the channel structure, the second gate conductive pattern disposed between the first gate conductive pattern and the bonding structure; and

a second gate contact structure disposed between the second gate conductive pattern and the first gate contact structure,

wherein the second gate contact structure includes a second vertical part penetrating the bonding structure and the first gate conductive pattern and a second horizontal part extending from the second vertical part, and

wherein a sidewall of the second horizontal part is in contact with the second gate conductive pattern.

4. The semiconductor memory device of claim 3 ,

wherein the first gate conductive pattern further protrudes toward the first gate contact structure than the second gate conductive pattern.

5. The semiconductor memory device of claim 3 , further comprising:

a first interlayer insulating layer surrounding the channel structure between the first gate conductive pattern and the second gate conductive pattern;

a second interlayer insulating layer overlapping with the first interlayer insulating layer with the first gate conductive pattern interposed between the second interlayer insulating layer and the first interlayer insulating layer, wherein the second interlayer insulating layer surrounds the channel structure; and

a second gate spacer insulating layer surrounding a sidewall of the second vertical part, wherein the second gate spacer insulating layer is penetrated by the second horizontal part,

wherein the first gate spacer insulating layer surrounds a sidewall of the first vertical part, fills the gap between the first gate conductive pattern and the first vertical part, and is penetrated by the first horizontal part.

6. The semiconductor memory device of claim 5 ,

wherein each of the first gate spacer insulating layer and the second gate spacer insulating layer protrudes toward the first gate conductive pattern to fill a gap between the first interlayer insulating layer and the second interlayer insulating layer.

7. The semiconductor memory device of claim 5 ,

wherein each of the first gate spacer insulating layer and the second gate spacer insulating layer includes a bottom surface which faces the peripheral circuit layer and overlaps with the bonding structure.

8. The semiconductor memory device of claim 1 , wherein the peripheral circuit layer includes:

a substrate including an impurity region;

an interconnection structure connected to the impurity region; and

a conductive pad connected to the interconnection structure and overlapping with the first vertical part.

9. The semiconductor memory device of claim 8 ,

wherein the first vertical part extends to be in contact with the conductive pad.