IP Library › Granted Patent US 11,656,967
Granted Patent B2
US 11,656,967 · App. 17/166,417 · Granted May 23, 2023

Method and apparatus for supporting persistence and computing device

Inventors: Myoungsoo Jung (Daejeon, KR); Miryeong Kwon (Daejeon, KR); Gyuyoung Park (Daejeon, KR); SangWon Lee (Daejeon, KR)
Assignees: MEMRAY CORPORATION; KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
G06F11/3037G06F1/28G06F1/30G06F9/30047G06F9/4881G06F11/1441G06F11/3058G06F12/0238
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Quick Facts
Patent No.
US 11,656,967
App. No.
17/166,417
Granted
May 23, 2023
Kind
B2
Abstract

A method of supporting persistence of a computing device is provided. The computing device performs a stop procedure upon power failure. In the stop procedure, the computing device schedules out a running process task, stores a state of the process task to a process control block of a memory module including a non-volatile memory, flushes a cache for the processor, and flushes a pending memory request.

Claims (37)

1. A method of supporting persistence of a computing device including a processor and a memory module including a non-volatile memory, the method comprising:

performing a stop procedure upon power failure, wherein the step of performing the stop procedure comprises

scheduling out a running process task,

storing a state of the process task to a process control block of the memory module,

flushing a cache for the processor, and

flushing a pending memory request;

wherein the processor includes a plurality of core tiles including a master tile and a worker tile, and

wherein the scheduling out the running process task comprises:

scheduling out a process task running on the master tile except a kernel process implementing the stop procedure; and

scheduling out a process task running on the worker tile.

2. The method of claim 1 , further comprising performing a go procedure when power is recovered,

wherein the performing the go procedure comprises scheduling process tasks based on the process control block.

3. The method of claim 2 , wherein the performing the stop procedure further comprises storing a register associated with a program for performing the stop procedure and the go procedure to the memory module.

4. The method of claim 3 , wherein the performing the go procedure further comprises restoring the register from the memory module.

5. The method of claim 1 , wherein the performing the stop procedure further comprises:

reading peripheral information from a peripheral related memory region; and

writing the peripheral information to a device context of the memory module.

6. The method of claim 5 , further comprising performing a go procedure when power is recovered,

wherein the performing the go procedure comprises restoring the peripheral information by reading the device context.

7. The method of claim 1 , wherein the performing the stop procedure comprises, after flushing the pending memory request;

reporting offline to the master tile and powering off, at the worker tile; and

switching a context at the master tile when receiving the offline report from the worker tile.

8. The method of claim 7 , wherein the switching the context comprises raising a system-level exception to switch the context from a kernel to bootloader of a protection mode.

9. The method of claim 8 , wherein the performing the stop procedure comprises, in the protection mode, storing a return address for re-executing a system to the memory module.

10. The method of claim 1 , wherein the performing the stop procedure comprises:

raising a system-level exception to switch a context from a kernel to bootloader of a protection mode; and

executing a first flush instruction for flushing the cache and a second flush instruction for flushing the memory request in the protection mode.

11. The method of claim 1 , wherein the flushing the cache comprises flushing the cache in a user-level without checking a memory region of the memory module.

12. A method of supporting persistence of a computing device including a processor and a memory module including a non-volatile memory, the method comprising:

performing a stop procedure upon power failure, wherein the step of performing the stop procedure comprises

scheduling out a running process task,

storing a state of the process task to a process control block of the memory module,

flushing a cache for the processor, and

flushing a pending memory request, wherein the step of scheduling out the running process task comprises replacing the running process task with an idle task; and

wherein the performing the stop procedure comprises clearing a kernel pointer of referring to the idle task.

13. The method of claim 12 , further comprising performing a go procedure when power is recovered,

wherein the performing the go procedure comprises scheduling process tasks based on the process control block after returning the kernel pointer to an idle task.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2021
From: JUNG, MYOUNGSOO; KWON, MIRYEONG; PARK, GYUYOUNG; LEE, SANGWON
To: MEMRAY CORPORATION; KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
Reel/Frame 055210/0402 →
Priority Claims (2)
KR 10-2020-0017925 · Feb 13, 2020 · national
KR 10-2020-0145403 · Nov 3, 2020 · national
Continuity (1)
Related Publication 20210255942A1 · Aug 19, 2021