PNP controlled ESD protection device with high holding voltage and snapback
View Patent ↗An ESD protection device protects a circuit from TLPs between a first terminal and a second terminal. The device includes an NPN discharge structure and a PNP triggering device. The first terminal is coupled to the p-doped emitter and the n-doped base of the PNP triggering device and also the n-doped emitter of the NPN discharge structure. The second terminal is coupled to the n-doped collector of the NPN discharge structure. The p-doped collector of the PNP triggering device is coupled to the p-doped base of the NPN discharge structure. A TLP causes base-collector junction breakdown in the PNP triggering device, which results in a current through the PNP triggering device. That current is injected into the base of the NPN discharge structure, which results in a larger discharge current through the NPN discharge structure. The device provides high holding voltage ESD protection device with snapback.
1. A method of forming an electrostatic discharge protection device on an integrated chip, the method comprising:
forming an NPN bipolar junction transistor in a semiconductor substrate, the NPN bipolar junction transistor comprising an n-doped emitter, a p-doped base, and an n-doped collector;
forming a PNP bipolar junction transistor in the semiconductor substrate, the PNP bipolar junction transistor comprising a p-doped emitter, an n-doped base, and a p-doped collector; and
forming a metal interconnect comprising:
a first metal structure that couples an anode terminal to the p-doped emitter, the n-doped base, and the n-doped emitter;
a second metal structure that couples a cathode terminal to the n-doped collector; and
a third metal structure that couples the p-doped collector to the p-doped base;
wherein the p-doped collector and the p-doped base are physically separated from one another.
2. The method of claim 1 , wherein the NPN bipolar junction transistor surrounds the PNP bipolar junction transistor.
3. A method of forming an integrated circuit with an electrostatic discharge protection device, the method comprising:
providing a p-doped semiconductor substrate with a buried n-doped layer;
forming a plurality of n-wells in the p-doped semiconductor substrate above the buried n-doped layer, wherein:
the plurality of n-wells extend to a depth of the buried n-doped layer;
the plurality of n-wells comprise one or more first n-wells, one or more second n-wells, one or more third n-wells, and one or more fourth n-wells;
a plurality of p-wells are provided by portions of the p-doped semiconductor substrate between neighboring members of the plurality of n-wells;
the plurality of p-wells comprise one or more first p-wells and one or more second p-wells;
the first p-wells abut the first n-wells; and
the second p-wells abut the third n-wells and the fourth n-wells;
doping to provide deep p-wells that isolate the fourth n-wells from the buried n-doped layer;
implanting p-type dopants to provide first collector contact regions directly above the first n-wells, first emitter contact regions directly above the first p-wells, and second base contact regions directly above the second p-wells;
implanting n-type dopants to provide first base contact regions directly above the second n-wells, second collector contact regions directly above the third n-wells, and second emitter contact regions directly above the fourth n-wells; and
forming a metal interconnect comprising:
a first metal structure that couples an anode terminal to the first collector contact regions, the first base contact regions, and the second collector contact regions;
a second metal structure that couples a cathode terminal to the second emitter contact regions; and
a third metal structure that couples the first emitter contact regions to the second base contact regions.
4. The method of claim 3 , further comprising forming shallow trench isolation structures at edges of the second n-wells, the third n-wells, and the fourth n-wells.
5. The method of claim 3 , further comprising covering edges of the first n-wells with resist protective oxide.
6. The method of claim 3 , further comprising doping to form more heavily n-doped areas in upper portions of the plurality of n-wells.
7. The method of claim 3 , wherein the third n-wells and the fourth n-wells surround the first n-wells.
8. The method of claim 7 , wherein the second n-wells surround the first n-wells.
9. The method of claim 3 , further comprising doping to form more heavily p-doped areas in upper portions of the plurality of p-wells.
10. The method of claim 3 , further comprising doping to form more heavily n-doped areas in upper portions of the plurality of n-wells.
11. The method of claim 3 , wherein:
the plurality of p-wells further comprises a third p-well;
the third p-well abuts one of the second n-wells or one of the third n-wells;
implanting p-type dopants provide p-doped contact region directly above the third p-wells; and
the second metal structure couples the cathode terminal to the p-doped contact region.
12. The method of claim 11 , wherein the third p-well abuts one of the second n-wells and one of the third n-wells.
13. The method of claim 3 , wherein:
the first p-wells have first widths;
the second p-wells have second widths; and
the second widths are different from the first widths.
14. The method of claim 3 , wherein the one or more first p-wells comprise at least three first p-wells.
15. A method of forming an integrated circuit with an electrostatic discharge protection device, the method comprising:
forming an n-doped buried layer in a semiconductor substrate;
doping the semiconductor substrate to form alternating and adjacent first n-wells and first p-wells in a first region, an adjacent second n-well and second p-well in a second region, and alternating and adjacent third n-wells and third p-wells in a third region, wherein the first n-wells, the first p-wells, the second n-well, the second p-well, third n-wells, and the third p-wells extend to a depth of the n-doped buried layer;
masking every other third n-well so that a first group of third n-wells is masked and a second group of third n-wells is unmasked;
doping to form deep p-wells under the second group of third n-wells while the first group of third n-wells, the first region, and the second region are masked;
doping to form n-doped contact regions directly over the second n-well and the third n-wells;
doping to form p-doped contact regions directly over the first n-wells, the first p-wells, the second p-well and the third p-wells; and
forming a metal interconnect connecting the p-doped contact regions over the first n-wells, the n-doped contact regions over the second n-well, and the n-doped contact regions over the first group of third n-wells to a first terminal, connecting the p-doped contact regions over the first p-wells and the p-doped contact regions over the third p-wells to each other, and connecting the p-doped contact regions over the second p-well and the n-doped contact regions over the second group of the third n-wells to a second terminal.
16. The method of claim 15 , wherein the third region surrounds the first region.
17. The method of claim 15 , wherein the second region is between the first region and the third region.
18. The method of claim 15 , further comprising forming shallow trench isolation structures at boundaries between the third n-wells and the third p-wells.
19. The method of claim 18 , further comprising forming oxide strips over the semiconductor substrate at boundaries between the first n-wells and the first p-wells.
20. The method of claim 15 , further comprising doping the semiconductor substrate to form first shallow n-wells over the first n-wells and first shallow p-wells over the first p-wells, wherein the first shallow p-wells have higher dopant concentration than the first p-wells and lower dopant concentration than the p-doped contact regions over the first p-wells.