IP Library › Granted Patent US 11,545,298
Granted Patent B2
US 11,545,298 · App. 17/169,118 · Granted Jan 3, 2023

Method of forming entangled inductor structures

Inventors: Ka Fai Chang (Hsinchu, TW); Chin-Chou Liu (Jhubei, TW); Fong-Yuan Chang (Hsinchu, TW); Hui Yu Lee (Hsinchu, TW); Yi-Kan Cheng (Taipei, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01F27/34H01F27/28H01F41/04H01L23/481H01L23/5227H01L23/5283H01L25/0657H01L25/50H01L28/10H01L2225/06541
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Quick Facts
Patent No.
US 11,545,298
App. No.
17/169,118
Granted
Jan 3, 2023
Kind
B2
Abstract

An entangled inductor structure generates opposite polarity internal magnetic fields therein to substantially reduce, or cancel, external magnetic fields propagating outside of the entangled inductor structure. These reduced external magnetic fields propagating outside of the entangled inductor structure effectively reduce a keep out zone (KOZ) between the entangled inductor structure and other electrical, mechanical, and/or electro-mechanical components. This allows the entangled inductor structure to be situated closer to these other electrical, mechanical, and/or electro-mechanical components within the IC as compared to conventional inductors which generate larger external magnetic fields.

Claims (97)

1. A method for forming an entangled inductor structure, the method comprising:

forming a first entangled current carrying structure from among a plurality of entangled current carrying structures onto a first semiconductor substrate from among a plurality of semiconductor substrates, the first entangled current carrying structure including a first plurality of entangled current carrying nodes,

wherein a first entangled current carrying node from among the first plurality of entangled current carrying nodes is situated adjacent to a second entangled current carrying node from among the first plurality of entangled current carrying nodes,

wherein the second entangled current carrying node is situated adjacent to a third entangled current carrying node from among the first plurality of entangled current carrying nodes,

wherein the third entangled current carrying node is situated adjacent to a fourth entangled current carrying node from among the first plurality of entangled current carrying nodes,

wherein the fourth entangled current carrying node is situated adjacent to the first entangled current carrying node,

wherein the first entangled current carrying node is electrically connected to the third entangled current carrying node,

wherein the second entangled current carrying node is electrically connected to the third entangled current carrying node and the fourth entangled current carrying node; and

forming a second entangled current carrying structure from among the plurality of entangled current carrying structures onto a second semiconductor substrate from among the plurality of semiconductor substrates, the second entangled current carrying structure including a second plurality of entangled current carrying nodes; and

connecting the first entangled current carrying structure to the second entangled current carrying structure to form the entangled inductor structure.

2. The method of claim 1 , wherein the forming the first entangled current carrying structure comprises:

forming a through silicon via (TSV) structure within the first semiconductor substrate that is electrically connected to the fourth entangled current carrying node, and

wherein the connecting comprises:

bonding the TSV structure to the second entangled current carrying structure to form the entangled inductor structure.

3. The method of claim 2 , wherein the forming the TSV structure comprises:

applying a photoresist to the first semiconductor substrate, the photoresist having an opening that exposes an area of the first semiconductor substrate;

performing an anisotropic etching process on the first semiconductor substrate to form the opening in the first semiconductor substrate; and

filling the opening with a conductive material to form the TSV structure.

4. The method of claim 2 , wherein the forming the first entangled current carrying structure further comprises:

forming a bump onto the first semiconductor substrate that is connected to the TSV structure, and

wherein the bonding comprises:

bonding the bump to the second entangled current carrying structure to form the entangled inductor structure.

5. The method of claim 1 , wherein the first plurality of entangled current carrying nodes and the second plurality of entangled current carrying nodes are implemented as a first plurality of open geometric rectangular geometric structures and a second plurality of open geometric rectangular geometric structures, respectively.

6. The method of claim 1 , wherein the forming the first entangled current carrying structure comprises:

forming the first entangled current carrying node, the second entangled current carrying node, the third entangled current carrying node, and the fourth entangled current carrying node within a first conductive layer;

forming a first interconnection between the first entangled current carrying node and the third entangled current carrying node within the first conductive layer to connect the first entangled current carrying node and the third entangled current carrying node;

forming a second interconnection between the second entangled current carrying node and the third entangled current carrying node within the first conductive layer to connect the second entangled current carrying node and the third entangled current carrying node;

forming a third interconnection between the second entangled current carrying node and the fourth entangled current carrying node within a second conductive layer;

forming a first via structure in at least one non-conductive layer that is situated between the first conductive layer and the second conductive layer to connect the third interconnection to the second entangled current carrying node; and

forming a second via structure in the at least one non-conductive layer to connect the third interconnection to the fourth entangled current carrying node.

7. The method of claim 1 , wherein the second entangled current carrying structure includes a second plurality of entangled current carrying nodes,

wherein a fifth entangled current carrying node from among the second plurality of entangled current carrying nodes is situated adjacent to a sixth entangled current carrying node from among the second plurality of entangled current carrying nodes,

wherein the sixth entangled current carrying node is situated adjacent to a seventh entangled current carrying node from among the second plurality of entangled current carrying nodes,

wherein the seventh entangled current carrying node is situated adjacent to an eighth entangled current carrying node from among the second plurality of entangled current carrying nodes,

wherein the eighth entangled current carrying node is situated adjacent to the fifth entangled current carrying node, and

wherein the connecting comprises:

connecting the fourth entangled current carrying node to the fifth entangled current carrying node to form the entangled inductor structure.

8. A method for forming an entangled inductor structure, the method comprising:

forming a first entangled current carrying structure, having a plurality of entangled current carrying nodes, from among a plurality of entangled current carrying structures onto a first semiconductor substrate from among a plurality of semiconductor substrates, the forming the first entangled current carrying structure comprising:

forming a first entangled current carrying node, a second entangled current carrying node, a third entangled current carrying node, and a fourth entangled current carrying node from among the first plurality of entangled current carrying nodes onto the first semiconductor substrate;

connecting the first entangled current carrying node to the third entangled current carrying node; and

connecting the second entangled current carrying node to the third entangled current carrying node and the fourth entangled current carrying node to form the first entangled current carrying structure;

forming a second entangled current carrying structure from among the plurality of entangled current carrying structures onto a second semiconductor substrate from among the plurality of semiconductor substrates; and

connecting the first entangled current carrying structure to the second entangled current carrying structure to form the entangled inductor structure.

9. The method of claim 8 , wherein the forming the first entangled current carrying structure further comprises:

forming a through silicon via (TSV) structure within the first semiconductor substrate that is electrically connected to the fourth entangled current carrying node, and

wherein the connecting the first entangled current carrying structure to the second entangled current carrying structure comprises:

bonding the TSV structure to the second entangled current carrying structure to form the entangled inductor structure.

10. The method of claim 9 , wherein the forming the TSV structure comprises:

applying a photoresist to the first semiconductor substrate, the photoresist having an opening that exposes an area of the first semiconductor substrate;

performing an anisotropic etching process on the first semiconductor substrate to form the opening in the first semiconductor substrate; and

filling the opening with a conductive material to form the TSV structure.

11. The method of claim 9 , wherein the forming the first entangled current carrying structure further comprises:

forming a bump onto the first semiconductor substrate that is connected to the TSV structure, and

wherein the bonding comprises:

bonding the bump to the second entangled current carrying structure to form the entangled inductor structure.

12. The method of claim 8 , wherein the first plurality of entangled current carrying nodes and the second plurality of entangled current carrying nodes are implemented as a first plurality of open geometric rectangular geometric structures and a second plurality of open geometric rectangular geometric structures, respectively.

13. The method of claim 8 , wherein the forming the first entangled current carrying structure further comprises:

forming the first entangled current carrying node, the second entangled current carrying node, the third entangled current carrying node, and the fourth entangled current carrying node within a first conductive layer;

forming a first interconnection between the first entangled current carrying node and the third entangled current carrying node within the first conductive layer to connect the first entangled current carrying node and the third entangled current carrying node;

forming a second interconnection between the second entangled current carrying node and the third entangled current carrying node within the first conductive layer to connect the second entangled current carrying node and the third entangled current carrying node;

forming a third interconnection between the second entangled current carrying node and the fourth entangled current carrying node within a second conductive layer;

forming a first via structure in at least one non-conductive layer that is situated between the first conductive layer and the second conductive layer to connect the third interconnection to the second entangled current carrying node; and

forming a second via structure in the at least one non-conductive layer to connect the third interconnection to the fourth entangled current carrying node.

14. The method of claim 8 , wherein the second entangled current carrying structure includes a second plurality of entangled current carrying nodes,

wherein a fifth entangled current carrying node from among the second plurality of entangled current carrying nodes is situated adjacent to a sixth entangled current carrying node from among the second plurality of entangled current carrying nodes,

wherein the sixth entangled current carrying node is situated adjacent to a seventh entangled current carrying node from among the second plurality of entangled current carrying nodes,

wherein the seventh entangled current carrying node is situated adjacent to an eighth entangled current carrying node from among the second plurality of entangled current carrying nodes,

wherein the eighth entangled current carrying node is situated adjacent to the fifth entangled current carrying node, and

wherein the connecting the first entangled current carrying structure to the second entangled current carrying structure comprises:

connecting the fourth entangled current carrying node to the fifth entangled current carrying node to form the entangled inductor structure.

15. A method for forming an entangled inductor structure, the method comprising:

forming a first entangled current carrying structure, having a plurality of entangled current carrying nodes, from among a plurality of entangled current carrying structures onto a first semiconductor substrate from among a plurality of semiconductor substrates, the forming the first entangled current carrying structure comprising:

forming a first entangled current carrying node, a second entangled current carrying node, a third entangled current carrying node, and a fourth entangled current carrying node from among the first plurality of entangled current carrying nodes onto the first semiconductor substrate;

forming a second entangled current carrying structure from among the plurality of entangled current carrying structures onto a second semiconductor substrate from among the plurality of semiconductor substrates, the forming the second entangled current carrying structure comprising:

forming a fifth entangled current carrying node, a sixth entangled current carrying node, a seventh entangled current carrying node, and an eighth entangled current carrying node from among the second plurality of entangled current carrying nodes onto the second semiconductor substrate; and

connecting the fourth entangled current carrying node to the fifth entangled current carrying node to form the entangled inductor structure.

16. The method of claim 15 , wherein the forming the first entangled current carrying structure comprises:

forming a through silicon via (TSV) structure within the first semiconductor substrate that is electrically connected to the fourth entangled current carrying node, and

wherein the connecting comprises:

bonding the TSV structure to the fifth entangled current carrying node to form the entangled inductor structure.

17. The method of claim 16 , wherein the forming the TSV structure comprises:

applying a photoresist to the first semiconductor substrate, the photoresist having an opening that exposes an area of the first semiconductor substrate;

performing an anisotropic etching process on the first semiconductor substrate to form the opening in the first semiconductor substrate; and

filling the opening with a conductive material to form the TSV structure.

18. The method of claim 16 , wherein the forming the first entangled current carrying structure further comprises:

forming a bump onto the first semiconductor substrate that is connected to the TSV structure, and

wherein the bonding comprises:

bonding the bump to the fifth entangled current carrying node to form the entangled inductor structure.

19. The method of claim 15 , wherein the first plurality of entangled current carrying nodes and the second plurality of entangled current carrying nodes are implemented as a first plurality of open geometric rectangular geometric structures and a second plurality of open geometric rectangular geometric structures, respectively.

20. The method of claim 15 , wherein the forming the first entangled current carrying structure comprises:

forming the first entangled current carrying node, the second entangled current carrying node, the third entangled current carrying node, and the fourth entangled current carrying node within a first conductive layer;

forming a first interconnection between the first entangled current carrying node and the third entangled current carrying node within the first conductive layer to connect the first entangled current carrying node and the third entangled current carrying node;

forming a second interconnection between the second entangled current carrying node and the third entangled current carrying node to within the first conductive layer connect the second entangled current carrying node and the third entangled current carrying node;

forming a third interconnection between the second entangled current carrying node and the fourth entangled current carrying node within a second conductive layer;

forming a first via structure in at least one non-conductive layer that is situated between the first conductive layer and the second conductive layer to connect the third interconnection to the second entangled current carrying node; and

forming a second via structure in the at least one non-conductive layer to connect the third interconnection to the fourth entangled current carrying node.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2021
From: CHANG, KA FAI; LIU, CHIN-CHOU; CHAN, FONG-YUAN; LEE, HUI YU; CHENG, YI-KAN
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 055168/0404 →
Continuity (3)
Division 16456025 · Jun 28, 2019
Provisional Application 62753228 · Oct 31, 2018
Related Publication 20210257156A1 · Aug 19, 2021