Semiconductor device with gate spacer and manufacturing method of the semiconductor device
The present application provides a semiconductor device with an air gate spacer for reducing parasitic capacitance and a method for manufacturing the semiconductor device. The semiconductor device includes a stacking structure, a first sidewall spacer and a second sidewall spacer. The stacking structure stands on a semiconductor substrate. The first and second sidewall spacers cover a sidewall of the stacking structure. An air gap is sealed between the first and second sidewall spacers. A top end of the air gap is substantially aligned with top ends of the first and second sidewall spacers. A top portion of the air gap is tapered toward a top end of the air gap.
1. A semiconductor device, comprising:
a stacking structure, standing on a semiconductor substrate; and
a first sidewall spacer and a second sidewall spacer, covering a sidewall of the stacking structure, wherein an air gap is sealed between the first and second sidewall spacers, topmost ends of the first sidewall spacer, the air gap, the second sidewall spacer and the stacking structure are coplanara, and a top portion of the air gap is tapered toward the topmost end of the air gap.
2. The semiconductor device according to claim 1 , wherein the air gap is substantially identical with the first and second sidewall spacers in terms of shape.
3. The semiconductor device according to claim 1 , wherein the air gap laterally spans from an outer sidewall of the first sidewall spacer to an inner sidewall of the second sidewall spacer.
4. The semiconductor device according to claim 1 , wherein the first and second sidewall spacers are respectively formed of a carbon-containing material.
5. The semiconductor device according to claim 4 , wherein the carbon-containing material comprises high density carbon (HDC), silicon carbide or silicon carbonitride.
6. The semiconductor device according to claim 1 , further comprising a liner layer enclosing the air gap.
7. The semiconductor device according to claim 6 , wherein the liner layer covers opposing sidewalls of the first and second sidewall spacers as well as a portion of the semiconductor substrate between the first and second sidewall spacers, and seals the top end of the air gap.
8. The semiconductor device according to claim 1 , wherein the stacking structure comprises:
a gate electrode, disposed over the semiconductor substrate; and
a gate dielectric layer, lying between the gate electrode and the semiconductor substrate.
9. The semiconductor device according to claim 8 , wherein the stacking structure further comprises a hard mask disposed on the gate electrode.
10. The semiconductor device according to claim 8 , further comprising:
source/drain structures, disposed in a surface region of the semiconductor substrate and located at opposite sides of the stacking structure; and
contact plugs, respectively standing on one of the source/drain structures, and electrically connected to the source/drain structures.
11. The semiconductor device according to claim 10 , wherein the contact plugs are laterally spaced apart from the stacking structure by the first and second sidewall spacers as well as the air gap.