IP Library Granted Patent US 11,108,235
Granted Patent B1
US 11,108,235 · App. 17/173,505 · Granted Aug 31, 2021

Double synchronous unified virtual oscillator control for grid-forming and grid-following power electronic converters

Inventors: M A Awal (Raleigh, NC); Iqbal Husain (Raleigh, NC)
Assignee: North Carolina State University
H02J3/24H02J3/0012H03B5/02
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Quick Facts
Patent No.
US 11,108,235
App. No.
17/173,505
Granted
Aug 31, 2021
Kind
B1
Abstract

A power electronic converter can utilize exemplary double synchronous unified virtual oscillator control (DSUVOC) logic or circuitry to convert direct current to alternating current that is input into a power grid. An exemplary DSUVOC controller of the present disclosure includes a double synchronous space vector oscillator component, a sequence extraction component, a fault detection component, a pre-synchronization component, a virtual impedance component, a terminal voltage compensation component, and/or an active damping component, wherein the double synchronous unified virtual oscillator controller is capable of controlling a grid following or a grid forming power electronic converter enabling synchronization and fault ride-through under both balanced and unbalanced conditions.

Claims (28)

1. A double synchronous unified virtual oscillator controller of a power electronic converter in a power grid, comprising:

a double synchronous space vector oscillator configured to generate a voltage vector output using feedback of an output current of the power electronic converter, the double synchronous space vector oscillator comprising a double sequence current reference generation component, a double sequence vector limiter component, a positive sequence space vector oscillator component, and a negative sequence space vector oscillator component;

a sequence extraction component that is configured to extract positive and negative sequence symmetrical components of the output current of the power electronic converter;

a fault detection component that is configured to detect and latch a fault condition based on the feedback of the output current of the power electronic converter or a grid voltage at a point-of-coupling of the power electronic converter with the power grid;

a virtual impedance component that is configured to achieve harmonic current suppression in the output current of the power electronic converter;

an observer based active damping component that is configured to achieve resonance damping in a high frequency range originating from a higher-order filter of the power electronic converter, wherein the higher-order filter is at least a second order filter;

a terminal voltage compensation component that is configured to compensate a voltage deviation due to the higher-order filter or other non-ideal effects of the power electronic converter; and

a pre-synchronization component that is configured to synchronize the double synchronous space vector oscillator with a terminal voltage of the power electronic converter at the point-of-coupling before being connected to the power grid,

wherein the double synchronous unified virtual oscillator controller is configured to control the power electronic converter for both grid forming and grid following operations.

2. The double synchronous unified virtual oscillator controller of claim 1 , wherein the higher-order filter comprises an LCL filter.

3. The double synchronous unified virtual oscillator controller of claim 1 , wherein the power electronic converter connects to the power grid via a static transfer switch.

4. The double synchronous unified virtual oscillator controller of claim 1 , wherein the double synchronous unified virtual oscillator controller is configured to provide grid synchronization in a grid-following mode of operation with bidirectional power flow control capability without using a phase-locked-loop.

5. The double synchronous unified virtual oscillator controller of claim 1 , wherein the double synchronous unified virtual oscillator controller is configured to provide DC bus voltage regulation in a grid-following mode of operation without a phase-locked-loop.

6. The double synchronous unified virtual oscillator controller of claim 1 , wherein the double synchronous unified virtual oscillator controller is configured to implement a grid forming mode of operation that implements a droop response for both grid connected and islanded operations.

7. The double synchronous unified virtual oscillator controller of claim 6 , wherein the double synchronous unified virtual oscillator controller is implemented using an error in voltage vector magnitude in a voltage magnitude correction term.

8. The double synchronous unified virtual oscillator controller of claim 6 , wherein the double synchronous unified virtual oscillator controller is implemented using an error in square of voltage vector magnitude in a voltage magnitude correction term.

9. The double synchronous unified virtual oscillator controller of claim 6 , wherein the double synchronous unified virtual oscillator controller is configured to generate a switching duty ratio based on a DC bus voltage measurement.

10. The double synchronous unified virtual oscillator controller of claim 6 , wherein the double synchronous unified virtual oscillator controller is configured to provide voltage regulation support without communication through a communication network.

11. The double synchronous unified virtual oscillator controller of claim 1 , wherein the double synchronous unified virtual oscillator controller is configured to enable grid synchronization of a grid following power electronic converter or a grid forming power electronic converter under balanced and unbalanced grid voltage conditions without operation of a phase-locked-loop.

12. The double synchronous unified virtual oscillator controller of claim 1 , wherein the double synchronous unified virtual oscillator controller is configured to enable a ride-through of balanced and unbalanced grid faults by limiting the output current of the power electronic converter without switching to a phase-locked-loop based back-up controller.

13. The double synchronous unified virtual oscillator controller of claim 1 , wherein the double synchronous unified virtual oscillator controller is configured to enable grid synchronization of the power electronic converter under variable grid impedance conditions without tuning of control parameters.

14. The double synchronous unified virtual oscillator controller of claim 1 , wherein the virtual impedance component is configured to suppress harmonic distortion in the output current of a grid-following power electronic converter or a grid-forming power electronic converter.

15. The double synchronous unified virtual oscillator controller of claim 1 , wherein the terminal voltage compensation component is configured to eliminate a voltage deviation caused by the higher-order filter of the power electronic converter.

16. The double synchronous unified virtual oscillator controller of claim 1 , wherein the double sequence vector limiter component is configured to limit a reference of the output current of the power electronic converter within limits allowable by power electronic converter hardware.

17. The double synchronous unified virtual oscillator controller of claim 1 , wherein the positive sequence space vector oscillator component and the negative sequence space vector oscillator component are configured to enable simultaneous synchronization with positive and negative sequence symmetrical components of the grid voltage without operation of a phase-locked-loop.

18. The double synchronous unified virtual oscillator controller of claim 1 , wherein active resistances in the positive and negative sequence space vector oscillator components are configured to enable over-current limiting protection under fault conditions.

19. The double synchronous unified virtual oscillator controller of claim 1 , wherein the pre-synchronization component is configured to achieve start-up in a grid-following power electronic converter or seamless islanded to grid connected transition in a grid forming power electronic converter without operation of a phase-locked-loop.

20. The double synchronous unified virtual oscillator controller of claim 1 , wherein the double sequence current reference generation component is configured to achieve different control objectives in the power electronic converter, wherein the different control objectives include at least one of constant real power flow, constant reactive power flow, or balanced output current.

Assignments (2)
CONFIRMATORY LICENSE Recorded Mar 1, 2022
From: NORTH CAROLINA STATE UNIVERSITY RALEIGH
To: NATIONAL SCIENCE FOUNDATION
Reel/Frame 059627/0049 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2021
From: AWAL, M A; HUSAIN, IQBAL
To: NORTH CAROLINA STATE UNIVERSITY
Reel/Frame 055573/0861 →
Continuity (1)
Provisional Application 62972791 · Feb 11, 2020
Cited By (7)
US 12,470,128 US 12,489,359 US 12,494,652 US 12,542,440 US 12,620,886 US 12,640,568 US 12,726,025