IP Library Granted Patent US 11,481,865
Granted Patent B2
US 11,481,865 · App. 17/173,643 · Granted Oct 25, 2022

Methods and apparatus for tensor object support in machine learning workloads

Inventors: Elina Kamenetskaya (Belmont, MA); Liang Li (San Diego, CA); Andrew Evan Gruber (Arlington, MA); Jeffrey Leger (Tyngsboro, MA); Balaji Calidas (San Diego, CA); Ruihao Zhang (San Diego, CA)
Assignee: QUALCOMM Incorporated
G06T1/60
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Quick Facts
Patent No.
US 11,481,865
App. No.
17/173,643
Granted
Oct 25, 2022
Kind
B2
Abstract

The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may modify at least one texture memory object to support a data structure for one or more tensor objects. The apparatus may also determine one or more supported memory layouts for the one or more tensor objects based on the modified at least one texture memory object. Additionally, the apparatus may access data associated with the one or more tensor objects based on the one or more supported memory layouts, the data for each of the one or more tensor objects corresponding to at least one data instruction. The apparatus may also execute the at least one data instruction based on the accessed data associated with the one or more tensor objects.

Claims (52)

1. A method of graphics processing, comprising:

modifying at least one texture memory object to support a data structure for one or more tensor objects, wherein the at least one texture memory object corresponds to a two-dimensional (2D) structure or a first three-dimensional (3D) structure, and wherein the one or more tensor objects correspond to a second three-dimensional (3D) structure or a four-dimensional (4D) structure;

determining one or more supported memory layouts for the one or more tensor objects based on the modified at least one texture memory object, wherein the one or more supported memory layouts are associated with at least one dimension, the at least one dimension including at least one of a width, a height, a feature, or a batch;

converting data associated with the one or more tensor objects based on the one or more supported memory layouts;

implementing the one or more supported memory layouts for the one or more tensor objects;

accessing the data associated with the one or more tensor objects based on the one or more supported memory layouts, the data for each of the one or more tensor objects corresponding to at least one data instruction; and

executing the at least one data instruction based on the accessed data associated with the one or more tensor objects.

2. The method of claim 1 , wherein modifying the at least one texture memory object includes at least one of rearranging the data associated with the one or more tensor objects or mapping the data associated with the one or more tensor objects.

3. The method of claim 1 , wherein the one or more supported memory layouts correspond to the data structure for the one or more tensor objects.

4. The method of claim 1 , wherein the one or more supported memory layouts are associated with one or more packing types for the one or more tensor objects.

5. The method of claim 1 , further comprising:

storing at least some of the data associated with the one or more tensor objects.

6. The method of claim 5 , wherein the at least some of the data is stored in one or more general purpose registers (GPRs) or on-chip memory.

7. The method of claim 1 , wherein executing the at least one data instruction comprises performing one or more operations, the one or more operations including at least one of a matrix multiplication operation or a convolution operation.

8. The method of claim 1 , wherein the at least one data instruction corresponds to code or shader code.

9. The method of claim 1 , wherein the data associated with the one or more tensor objects is accessed based on at least one request for the data.

10. The method of claim 1 , wherein the data associated with the one or more tensor objects is accessed by a shader processor (SP) or a texture processor (TP).

11. The method of claim 1 , wherein the at least one data instruction is executed based on a machine learning application or a neural network (NN).

12. An apparatus for graphics processing, comprising:

a memory; and

at least one processor coupled to the memory and configured to:

modify at least one texture memory object to support a data structure for one or more tensor objects, wherein the at least one texture memory object corresponds to a two-dimensional (2D) structure or a first three-dimensional (3D) structure, and wherein the one or more tensor objects correspond to a second three-dimensional (3D) structure or a four-dimensional (4D) structure;

determine one or more supported memory layouts for the one or more tensor objects based on the modified at least one texture memory object, wherein the one or more supported memory layouts are associated with at least one dimension, the at least one dimension including at least one of a width, a height, a feature, or a batch;

convert data associated with the one or more tensor objects based on the one or more supported memory layouts;

implement the one or more supported memory layouts for the one or more tensor objects;

access the data associated with the one or more tensor objects based on the one or more supported memory layouts, the data for each of the one or more tensor objects corresponding to at least one data instruction; and

execute the at least one data instruction based on the accessed data associated with the one or more tensor objects.

13. The apparatus of claim 12 , wherein to modify the at least one texture memory object includes at least one of rearranging the data associated with the one or more tensor objects or mapping the data associated with the one or more tensor objects.

14. The apparatus of claim 12 , wherein the one or more supported memory layouts correspond to the data structure for the one or more tensor objects.

15. The apparatus of claim 12 , wherein the one or more supported memory layouts are associated with one or more packing types for the one or more tensor objects.

16. The apparatus of claim 12 , wherein the at least one processor is further configured to:

store at least some of the data associated with the one or more tensor objects.

17. The apparatus of claim 16 , wherein the at least some of the data is stored in one or more general purpose registers (GPRs) or on-chip memory.

18. The apparatus of claim 12 , wherein to execute the at least one data instruction comprises the at least one processor configured to perform one or more operations, the one or more operations including at least one of a matrix multiplication operation or a convolution operation.

19. The apparatus of claim 12 , wherein the at least one data instruction corresponds to code or shader code.

20. The apparatus of claim 12 , wherein the data associated with the one or more tensor objects is accessed based on at least one request for the data.

21. The apparatus of claim 12 , wherein the data associated with the one or more tensor objects is accessed by a shader processor (SP) or a texture processor (TP).

22. The apparatus of claim 12 , wherein the at least one data instruction is executed based on a machine learning application or a neural network (NN).

23. An apparatus for graphics processing, comprising:

means for modifying at least one texture memory object to support a data structure for one or more tensor objects, wherein the at least one texture memory object corresponds to a two-dimensional (2D) structure or a first three-dimensional (3D) structure, and wherein the one or more tensor objects correspond to a second three-dimensional (3D) structure or a four-dimensional (4D) structure;

means for determining one or more supported memory layouts for the one or more tensor objects based on the modified at least one texture memory object, wherein the one or more supported memory layouts are associated with at least one dimension, the at least one dimension including at least one of a width, a height, a feature, or a batch;

means for converting data associated with the one or more tensor objects based on the one or more supported memory layouts;

means for implementing the one or more supported memory layouts for the one or more tensor objects;

means for accessing the data associated with the one or more tensor objects based on the one or more supported memory layouts, the data for each of the one or more tensor objects corresponding to at least one data instruction; and

means for executing the at least one data instruction based on the accessed data associated with the one or more tensor objects.

24. A non-transitory computer-readable medium storing computer executable code for graphics processing, the code when executed by a processor causes the processor to:

modify at least one texture memory object to support a data structure for one or more tensor objects, wherein the at least one texture memory object corresponds to a two-dimensional (2D) structure or a first three-dimensional (3D) structure, and wherein the one or more tensor objects correspond to a second three-dimensional (3D) structure or a four-dimensional (4D) structure;

determine one or more supported memory layouts for the one or more tensor objects based on the modified at least one texture memory object, wherein the one or more supported memory layouts are associated with at least one dimension, the at least one dimension including at least one of a width, a height, a feature, or a batch;

convert data associated with the one or more tensor objects based on the one or more supported memory layouts;

implement the one or more supported memory layouts for the one or more tensor objects;

access the data associated with the one or more tensor objects based on the one or more supported memory layouts, the data for each of the one or more tensor objects corresponding to at least one data instruction; and

execute the at least one data instruction based on the accessed data associated with the one or more tensor objects.

Assignments (2)
CONFIRMATORY LICENSE Recorded Jan 31, 2024
From: CHILDREN'S HOSPITAL (COLUMBUS)
To: NATIONAL INSTITUTES OF HEALTH - DIRECTOR DEITR
Reel/Frame 066306/0621 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2021
From: KAMENETSKAYA, ELINA; LI, LIANG; GRUBER, ANDREW EVAN; LEGER, JEFFREY; CALIDAS, BALAJI; ZHANG, RUIHAO
To: QUALCOMM INCORPORATED
Reel/Frame 055567/0440 →
Continuity (1)
Related Publication 20220253969A1 · Aug 11, 2022
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