Semiconductor package including a wire and a method of fabricating the semiconductor package

1. A semiconductor package comprising:

a chip stack mounted on a package substrate;

an outer wire disposed on the package substrate, wherein the outer wire includes a first unit outer wire; and

a molding layer surrounding the chip stack and the outer wire,

wherein the first unit outer wire includes a first segment and a second segment, wherein the first segment is in contact with the second segment to form an acute angle adjacent to a point at which the first and second segments intersect,

wherein the outer wire includes a second unit outer wire stacked over the first unit outer wire,

wherein the second unit outer wire includes a third segment and a fourth segment,

wherein the third segment intersects with the fourth segment to form an acute angle adjacent to a point at which the first and second segments intersect, and

wherein the second segment of the first unit outer wire intersects with the third segment of the second unit outer wire to form an acute angle adjacent to a point at which the second segment of the first unit outer wire intersects with the third segment of the second unit outer wire.

2. The semiconductor package of claim 1 ,

wherein the outer wire includes at least two first unit outer wires vertically staked over one another, and

wherein each of the at least two first unit outer wires includes the first segment and the second segment, wherein the first segment is in contact with the second segment to form an acute angle adjacent to a point at which the first and second segments intersect.

3. The semiconductor package of claim 2 ,

wherein the at least two first unit outer wires are arranged along a vertical direction and are space apart from each other in the vertical direction.

4. The semiconductor package of claim 1 ,

wherein the first segment of the first unit outer wire and the third segment of the second unit outer wire have a negative (−) slope and the second segment of the first unit outer wire and the fourth segment of the second unit outer wire have a positive (+) slope.

5. A semiconductor package comprising:

a chip stack mounted over a package substrate;

a first wire disposed over the package substrate; and

a molding layer surrounding the chip stack and the first wire,

wherein the first wire has a zigzag form,

wherein the first wire includes a plurality of unit wires arranged along a vertical direction, and

wherein each of the plurality of unit wires includes two diagonal shaped segments having a positive (+) slope and a negative (−) slope.

6. The semiconductor package of claim 5 ,

wherein the plurality of unit wires are arranged to be spaced apart from each other in the vertical direction.

7. The semiconductor package of claim 5 ,

wherein side ends of the plurality of the unit wires are exposed on a side surface of the molding layer.

8. The semiconductor package of claim 5 ,

wherein a top end of the first wire is exposed on a top surface of the molding layer.

9. The semiconductor package of claim 5 ,

wherein the package substrate includes a chip area and a peripheral area surrounding the chip area,

wherein the chip stack is disposed in the chip area, and

wherein the first wire is disposed in the peripheral area.

10. The semiconductor package of claim 9 , further comprising:

a second wire over the package substrate,

wherein the second wire vertically uprightly erects from a top surface of the package substrate.

11. The semiconductor package of claim 10 ,

wherein the peripheral area includes an inner peripheral area and an outer peripheral area surrounding the inner peripheral area,

wherein the first wire is disposed in the outer peripheral area, and

wherein the second wire is disposed in the inner peripheral area.

12. The semiconductor package of claim 10 ,

wherein a top end of the second wire is exposed on a top surface of the molding layer.

13. The semiconductor package of claim 10 ,

wherein the package substrate further includes a substrate via and a substrate interconnection electrically connected to the second wire.

14. The semiconductor package of claim 5 , further comprising:

a thermal interface material layer disposed over a top surface of the molding layer and a heat sink disposed over the thermal interface material layer,

wherein the thermal interface material layer is in contact with a top end of the first wire.

15. The semiconductor package of claim 5 , further comprising:

a shield layer formed over a top surface and a side surface of the molding layer,

wherein the shield layer is in contact with a side end of the first wire.

16. A semiconductor package comprising:

a chip stack mounted over a package substrate;

a first wire disposed over the package substrate;

a molding layer surrounding the chip stack and the first wire; and a first wire pad,

wherein the peripheral area includes an inner peripheral area and an outer peripheral area surrounding the inner peripheral area,

wherein the first wire pad is disposed in the outer peripheral area,

wherein the first wire is disposed over the first wire pad,

wherein a side surface of the first wire pad is exposed on a side surface of the molding layer.

17. The semiconductor package of claim 16 ,

wherein the side surface of the first wire pad and the side surface of the molding layer are vertically co-planar.