3D semiconductor device and structure with memory
A 3D semiconductor device including: a first level including a first single-crystal layer, a plurality of first transistors, and at least one metal layer, the metal layer overlaying the first single crystal layer with interconnects between the first transistors forming control circuits; a second level overlaying the metal layer, a plurality of second transistors, and a plurality of first memory cells including at least one of the second transistors; a third level overlaying the second level and including a plurality of third transistors, including second memory cells each including at least one third transistor, where at least one of the second memory cells is at least partially atop of the control circuits, where the control circuits are connected so to control second transistors and third transistors, where the second level is bonded to the third level, where the bonded includes oxide to oxide bonds; and a fourth level above the third level, including a second single-crystal layer.
1. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer, said first level comprising a plurality of first transistors and at least one metal layer,
wherein said at least one metal layer overlays said first single crystal layer, and
wherein said at least one metal layer comprises interconnects between said first transistors forming first control circuits;
a second level overlaying said at least one metal layer, said second level comprising a plurality of second transistors;
a third level overlaying said second level, said third level comprising a plurality of third transistors,
wherein said second level comprises a plurality of first memory cells, said first memory cells each comprising at least one of said second transistors,
wherein said third level comprises a plurality of second memory cells, said second memory cells each comprising at least one of said third transistors,
wherein at least one of said second memory cells is at least partially atop of said control circuits,
wherein said first control circuits are connected so to control at least one of said second transistors and at least one of said third transistors,
wherein said second level is bonded to said third level,
wherein said second level is bonded to said first level,
wherein said bonded comprises oxide to oxide bonds; and
a fourth level disposed above said third level,
wherein said fourth level comprises a second single crystal layer.
2. The 3D semiconductor device according to claim 1 ,
wherein said first control circuits comprise memory peripheral circuits comprising a plurality of decoders.
3. The 3D semiconductor device according to claim 1 ,
wherein said second transistors are aligned to said first transistors with less than 450 nm misalignment.
4. The 3D semiconductor device according to claim 1 ,
wherein said first memory cells are controlled thru a plurality of memory control lines, and
wherein said third level comprises at least one of said memory control lines.
5. The 3D semiconductor device according to claim 1 , further comprising:
at least one connecting via through said first single crystal layer.
6. The 3D semiconductor device according to claim 1 ,
wherein said plurality of second memory cells are DRAM memory cells.
7. The 3D semiconductor device according to claim 1 ,
wherein said fourth level comprises second control circuits.
8. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer, said first level comprising a plurality of first transistors and at least one metal layer,
wherein said at least one metal layer overlays said first single crystal layer, and
wherein said at least one metal layer comprises interconnects between said first transistors forming first control circuits;
a second level overlaying said at least one metal layer, said second level comprising a plurality of second transistors;
a third level overlaying said second level, said third level comprising a plurality of third transistors,
wherein said second level comprises a plurality of first memory cells, said first memory cells each comprising at least one of said second transistors,
wherein said third level comprises a plurality of second memory cells, said second memory cells each comprising at least one of said third transistors,
wherein at least one of said second memory cells is at least partially atop of said first control circuits,
wherein said first control circuits are connected so to control at least one of said second transistors and at least one of said third transistors,
wherein said second level is bonded to said third level,
wherein said bonded comprises oxide to oxide bonds; and
a fourth level disposed above said third level,
wherein said fourth level comprises a second single crystal layer, and
wherein said fourth level comprises second control circuits.
9. The 3D semiconductor device according to claim 8 ,
wherein said first control circuits and said second control circuits comprise memory peripheral circuits comprising a plurality of decoders.
10. The 3D semiconductor device according to claim 8 ,
wherein said second transistors are aligned to said first transistors with less than 450 nm misalignment.
11. The 3D semiconductor device according to claim 8 ,
wherein said first memory cells are controlled thru a plurality of memory control lines, and
wherein said third level comprises at least one of said memory control lines.
12. The 3D semiconductor device according to claim 8 ,
wherein said second level comprises a third single crystal layer.
13. The 3D semiconductor device according to claim 8 ,
wherein said plurality of second memory cells are DRAM memory cells.
14. The 3D semiconductor device according to claim 8 ,
wherein said second level is bonded to said first level, and
wherein said bonded comprises oxide to oxide bonds.
15. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer, said first level comprising a plurality of first transistors and at least one metal layer,
wherein said at least one metal layer overlays said first single crystal layer, and
wherein said at least one metal layer comprises interconnects between said first transistors forming control circuits;
a second level overlaying said at least one metal layer, said second level comprising a plurality of second transistors;
a third level overlaying said second level, said third level comprising a plurality of third transistors,
wherein said second level comprises a plurality of first memory cells, said first memory cells each comprising at least one of said second transistors,
wherein said third level comprises a plurality of second memory cells, said second memory cells each comprising at least one of said third transistors,
wherein at least one of said second memory cells is at least partially atop of said control circuits,
wherein said control circuits are connected so to control at least one of said second transistors and at least one of said third transistors,
wherein said second level is bonded to said third level,
wherein said bonded comprises oxide to oxide bonds; and
a fourth level disposed above said third level,
wherein said fourth level comprises a second single crystal layer.
16. The 3D semiconductor device according to claim 15 ,
wherein said control circuits comprise memory peripheral circuits comprising a plurality of decoders.
17. The 3D semiconductor device according to claim 15 ,
wherein said second transistors are aligned to said first transistors with less than 450 nm misalignment.
18. The 3D semiconductor device according to claim 15 ,
wherein said second level is bonded to said first level, and
wherein said bonded comprises oxide to oxide bonds.
19. The 3D semiconductor device according to claim 15 , further comprising:
at least one connecting via disposed through said first single crystal layer.
20. The 3D semiconductor device according to claim 15 ,
wherein said plurality of second memory cells are DRAM memory cells.