LIGHT EMITTING DIODE CONTAINING PINHOLE MASKING LAYER AND METHOD OF MAKING THEREOF

1 . A light emitting diode (LED), comprising:

a semiconductor buffer layer;

a n-doped semiconductor material layer;

a dielectric masking layer having a thickness of 20 nm or less and containing pinholes having a width of 200 nm or less filled with the n-doped semiconductor material of the n-doped semiconductor layer located between the semiconductor buffer layer and the n-doped semiconductor material layer;

a p-doped semiconductor material layer; and

an active region disposed between the n-doped semiconductor layer and the p-doped semiconductor layer.

2 . The LED of claim 1 , wherein the pinholes are randomly distributed laterally along the dielectric masking layer and a distance between nearest neighbor pinholes varies randomly laterally along the dielectric masking layer.

3 . The LED of claim 1 , wherein the pinholes are orderly distributed laterally along the dielectric masking layer.

4 . The LED of claim 1 , wherein the pinholes extend through an entire thickness of the dielectric masking layer, such that the n-doped semiconductor material of the n-doped semiconductor layer located in the pinholes contacts the semiconductor buffer layer.

5 . The LED of claim 4 , wherein the semiconductor buffer layer and the n-doped semiconductor material layer comprise a III-nitride semiconductor material.

6 . The LED of claim 5 , wherein the semiconductor buffer layer comprises undoped gallium nitride and the n-doped semiconductor material layer comprises n-doped gallium nitride.

7 . The LED of claim 5 , wherein the dielectric masking layer comprises aluminum oxide.

8 . The LED of claim 5 , wherein the dielectric masking layer comprises silicon nitride.

9 . The LED of claim 1 , further comprising a stack of dielectric masking layers containing pinholes.

10 . The LED of claim 1 , wherein the dielectric masking layer has a thickness of 1 to 20 nm and the pinholes have a width of 0.1 to 20 nm.

11 . A method of forming a light emitting diode (LED), comprising:

forming a buffer layer over a support substrate;

forming a dielectric masking layer having a thickness of 20 nm or less and containing pinholes having a width of 200 nm or less on the semiconductor buffer layer;

forming a n-doped semiconductor material layer on the dielectric masking layer such that the n-doped semiconductor material of the n-doped semiconductor layer fills the pinholes and contacts the buffer layer;

forming an active region over the n-doped semiconductor material layer; and

forming a p-doped semiconductor material layer over the active region.

12 . The method of claim 11 , wherein the dielectric masking layer is grown by atomic layer deposition (ALD) such that the pinholes are formed spontaneously during the ALD growth without using lithography and etching.

13 . The method of claim 12 , wherein the pinholes are randomly distributed laterally along the dielectric masking layer, such that a distance between nearest neighbor pinholes varies randomly laterally along the dielectric masking layer.

14 . The method of claim 12 , wherein the pinholes have a width of 0.1 to 20 nm and the dielectric masking layer has a thickness of 1 to 20 nm.

15 . The method of claim 12 , wherein:

the support substrate comprises a C-plane sapphire substrate having a (0001) top surface;

the semiconductor buffer layer comprises a III-nitride semiconductor material grown on the (0001) top surface of the sapphire substrate;

the n-doped semiconductor material layer comprises a III-nitride semiconductor material; and

the dielectric masking layer comprises aluminum oxide or silicon nitride.

16 . The method of claim 15 , wherein:

the semiconductor buffer layer comprises undoped gallium nitride;

the n-doped semiconductor material layer comprises n-doped gallium nitride; and

the dielectric masking layer comprises aluminum oxide.

17 . The method of claim 12 , wherein dislocations extend vertically in the semiconductor buffer layer from the support substrate and terminate at a bottom surface of the dielectric masking layer.

18 . The method of claim 12 , wherein the ALD growth of the dielectric masking layer occurs at a temperature greater than 125° C. and the thickness of the dielectric masking layer is 1 to 3 nm.

19 . The method of claim 12 , wherein the ALD growth of the dielectric masking layer occurs at a temperature of 80 to 120° C. and the thickness of the dielectric masking layer is 1 to 2 nm.

20 . The method of claim 12 , wherein the ALD growth of the dielectric masking layer and epitaxial growth of the n-doped semiconductor material layer by metal organic chemical vapor deposition occurs without breaking vacuum in a same deposition chamber or in different deposition chambers of a same vacuum cluster tool.

21 . A structure, comprising:

a first material layer;

a second material layer; and

a dielectric masking layer having a thickness of 20 nm or less and containing pinholes having a width of 200 nm or less filled with the second material of second material layer located between the first material layer and the second material layer.

22 . A method, comprising:

forming a first material layer;

forming a dielectric masking layer having a thickness of 20 nm or less and containing pinholes having a width of 200 nm or less on the first material layer; and

forming a second material layer on the dielectric masking layer such that the second material of the second material layer fills the pinholes and contacts the first material layer.