Partial discharge suppression in high voltage solid-state devices

1. A solid-state device, comprising:

a substrate;

a first electrical contact positioned on the substrate; and

a multi-layer encapsulation film at least partially surrounding the first electrical contact and the substrate, wherein the multi-layer encapsulation film comprises multiple layers of one or more dielectric materials, wherein an interface between two adjacent layers of the multiple layers is configured to include molecular bonds to prevent charge carriers from crossing between the two adjacent layers, and wherein the multi-layer encapsulation film comprises a semi-conductive material positioned between two of the multiple layers.

2. The solid-state device of claim 1 , wherein the one or more dielectric materials comprise at least one of polyimide, epoxy resin, or silicone gel.

3. The solid-state device of claim 1 , wherein the multiple layers comprise the same dielectric material.

4. The solid-state device of claim 1 , wherein the multiple layers comprise different dielectric materials.

5. The solid-state device of claim 1 , wherein a thickness of each of the multiple layers is smaller than 1 millimeter.

6. The solid-state device of claim 1 , wherein a number of layers of the multiple layers in the multi-layer encapsulation film is determined based on an operating voltage of the solid-state device.

7. The solid-state device of claim 1 , further comprising a semi-conductive coating positioned between the first electrical contact and the multi-layer encapsulation film.

8. The solid-state device of claim 1 , wherein the substrate comprises a wide band gap semiconductor material.

9. The solid-state device of claim 1 , wherein the substrate comprises separately doped semiconductor materials that form an electrical junction.

10. The solid-state device of claim 1 , further comprising a second electrical contact that is at least partially surrounded by the multi-layer encapsulation film, wherein the first electrical contact and the second electrical contact are arranged in a series configuration.

11. The solid-state device of claim 1 , wherein charge carriers in the substrate of the solid-state device are inhibited from crossing into a layer of the multiple layers due to the molecular bonds at an interface between the substrate and the layer.

12. A multi-layer encapsulation configuration for use in a solid-state device, comprising:

a first layer of a first dielectric material,

a second layer of a second dielectric material, wherein an interface between the first layer and the second layer is configured to include molecular bonds to prevent charge carriers from crossing between the first layer and the second layer, and wherein the multi-layer encapsulation configuration is structured to allow an electrical contact and a substrate of the solid-state device to be at least partially surrounded by the multi-layer encapsulation configuration, and

a semi-conductive material positioned between the first layer and the second layer.

13. The multi-layer encapsulation configuration of claim 12 , wherein the first dielectric material comprises at least one of polyimide, epoxy resin, or silicone gel.

14. The multi-layer encapsulation configuration of claim 12 , wherein the second dielectric material comprises at least one of polyimide, epoxy resin, or silicone gel.

15. The multi-layer encapsulation configuration of claim 12 , wherein the first dielectric material is same as the second dielectric material.

16. The multi-layer encapsulation configuration of claim 12 , wherein the first dielectric material is different than the second dielectric material.

17. The multi-layer encapsulation configuration of claim 12 , wherein a thickness of the first layer or the second layer is smaller than 1 millimeter.

18. The multi-layer encapsulation configuration of claim 12 , wherein the multi-layer encapsulation configuration is implemented as part of the solid-state device.

19. The multi-layer encapsulation configuration of claim 18 , wherein the solid-state device comprises separately doped semiconductor materials that form an electrical junction.

20. The multi-layer encapsulation configuration of claim 18 , wherein the solid-state device comprises a wide band gap semiconductor material.

21. A method for providing a multi-layer encapsulation configuration for use in a solid-state device, comprising:

depositing a first layer of a first dielectric material on an electrical contact of the solid-state device, wherein the electrical contact is positioned on a substrate of the solid-state device, and wherein the first layer at least partially surrounds the electrical contact and the substrate;

curing at least partially the first layer of the first dielectric material; and

depositing a second layer of a second dielectric material on the first layer of the first dielectric material, wherein molecular bonds formed at an interface between the first layer and the second layer are configured to prevent charge carriers from crossing between the first layer and the second layer,

the method further comprising:

depositing a semi-conductive material between two adjacent layers of the multi-layer encapsulation configuration.

22. The method of claim 21 , wherein the first dielectric material is same as the second dielectric material.

23. The method of claim 21 , wherein a thickness of the first layer and the second layer is smaller than 1 millimeter.

24. The method of claim 21 , comprising:

repeatedly depositing subsequent layers on the second layer, wherein a total number of layers in the multi-layer encapsulation configuration is determined based on an operating voltage of the solid-state device.