Intelligent architecture for actuator motor drive powered from wide-input high-voltage direct current
An intelligent architecture system is provided. The intelligent architecture system includes an input line, an output line and an intelligent architecture operably interposed between the input line and the output line. The intelligent architecture is configured to control a voltage of the output line in accordance with a voltage of the input line.
1. An intelligent architecture system, comprising:
an input line;
an output line; and
an intelligent architecture operably interposed between the input line and the output line,
the intelligent architecture being configured to control a voltage of the output line in accordance with a voltage of the input line, the intelligent architecture comprising:
a main line connected at an upstream end thereof to the input line and at a downstream end thereof to the output line;
a voltage limiter disposed along the main line to control the voltage of the output line;
a logic selector;
a pulse width modulation, PWM, generator to drive an operation of the voltage limiter in accordance with a signal from the logic selector;
first and second bypass lines connected at respective opposite ends thereof with the upstream and downstream ends of the main line, respectively, and with the logic selector; and
an input voltage sensing unit and an inrush control unit disposed along the first bypass line and an output voltage sensing unit and a high voltage control unit disposed along the second bypass line whereby the logic selector receives inputs from the first and second bypass lines on which the signal is based,
wherein the intelligent architecture is operable in various modes in accordance with the voltage of the input line, and wherein:
the logic selector receives an S 2 signal from the inrush control unit, which is based on an S 1 signal from the input voltage sensing unit, the S 2 signal being an instruction to initiate or not initiate an inrush current limiting mode of the voltage limiter if the input voltage sensing unit determines that a voltage of the inrush current is or is not steadily increasing from 0 volts to a nominal minimum voltage,
the logic selector receives an S 4 signal from the high voltage control unit, which is based on an S 3 signal from the output voltage sensing unit, the S 4 signal being an instruction to initiate or not initiate a DC link voltage limiting mode if the output voltage sensing unit determines that a voltage of the output voltage is or is not above a nominal maximum voltage, and
when:
the signal S 2 is the instruction to initiate the inrush current limiting mode, the logic selector and the PWM generator cooperatively cause the voltage limiter to operate in an inrush current limiting mode,
the signal S 4 is the instruction to initiate the DC link voltage limiting mode, the logic selector and the PWM generator cooperatively cause the voltage limiter to operate in a DC link voltage limiting mode, and
the signals S 2 and S 4 are both the instructions to not initiate the inrush current limiting mode or the DC link voltage limiting mode, the logic selector and the PWM generator cooperatively cause the voltage limiter to operate in an input voltage bypass mode.
2. The intelligent architecture system according to claim 1 , wherein the intelligent architecture is operable in an inrush current limiting mode until the voltage of the input line reaches a nominal minimum.
3. The intelligent architecture system according to claim 1 , wherein, when the voltage of the input line exceeds a nominal maximum, the intelligent architecture is operable in a DC link voltage limiting mode.
4. The intelligent architecture system according to claim 1 , wherein the intelligent architecture is operable in an input voltage bypass mode when the voltage of the input line exceeds a nominal minimum other than during a ramp-up stage.
5. An intelligent architecture system, comprising:
an input line;
an output line; and
an intelligent architecture operably interposed between the input line and the output line,
the intelligent architecture being configured to operate in various modes in accordance with the voltage of the input line to thereby control a voltage of the output line in accordance with the voltage of the input line, the intelligent architecture comprising:
a main line connected at an upstream end thereof to the input line and at a downstream end thereof to the output line;
a voltage limiter disposed along the main line to control the voltage of the output line;
a logic selector;
a pulse width modulation, PWM, generator to drive an operation of the voltage limiter in accordance with a signal from the logic selector;
first and second bypass lines connected at respective opposite ends thereof with the upstream and downstream ends of the main line, respectively, and with the logic selector; and
an input voltage sensing unit and an inrush control unit disposed along the first bypass line and an output voltage sensing unit and a high voltage control unit disposed along the second bypass line whereby the logic selector receives inputs from the first and second bypass lines on which the signal is based,
wherein the intelligent architecture is operable in an inrush current limiting mode until the voltage of the input line reaches a nominal minimum, and wherein:
the logic selector receives an S 2 signal from the inrush control unit, which is based on an S 1 signal from the input voltage sensing unit, the S 2 signal being an instruction to initiate or not initiate an inrush current limiting mode of the voltage limiter if the input voltage sensing unit determines that a voltage of the inrush current is or is not steadily increasing from 0 volts to a nominal minimum voltage,
the logic selector receives an S 4 signal from the high voltage control unit, which is based on an S 3 signal from the output voltage sensing unit, the S 4 signal being an instruction to initiate or not initiate a DC link voltage limiting mode if the output voltage sensing unit determines that a voltage of the output voltage is or is not above a nominal maximum voltage, and
when:
the signal S 2 is the instruction to initiate the inrush current limiting mode, the logic selector and the PWM generator cooperatively cause the voltage limiter to operate in an inrush current limiting mode,
the signal S 4 is the instruction to initiate the DC link voltage limiting mode, the logic selector and the PWM generator cooperatively cause the voltage limiter to operate in a DC link voltage limiting mode, and
the signals S 2 and S 4 are both the instructions to not initiate the inrush current limiting mode or the DC link voltage limiting mode, the logic selector and the PWM generator cooperatively cause the voltage limiter to operate in an input voltage bypass mode.
6. The intelligent architecture system according to claim 5 , wherein, when the voltage of the input line exceeds a nominal maximum, the intelligent architecture is operable in a DC link voltage limiting mode.
7. The intelligent architecture system according to claim 5 , wherein the intelligent architecture is operable in an input voltage bypass mode when the voltage of the input line exceeds a nominal minimum other than during a ramp-up stage.