Semiconductor memory device
A semiconductor memory device includes a memory cell including a switching element and a resistance change element. A first circuit supplies a constant current to the memory cell for an amount of time and a second circuit applies a constant voltage to the memory cell for an amount of time. The semiconductor memory device places the memory cell into an ON state by applying, while applying a first current to the memory cell by the first circuit, a first voltage to the memory cell by the second circuit and performs readout on the memory cell in the ON state by the first current.
1. A semiconductor memory device, comprising:
a memory cell comprising a switching element and a resistance change element;
a preamplifier coupled to the memory cell via a bit line; and
an amplifier coupled to the preamplifier,
wherein:
the preamplifier includes:
a first circuit that supplies a constant current to the memory cell via the bit line for an amount of time; and
a second circuit that applies a constant voltage to the memory cell via the bit line for an amount of time,
the first circuit and the second circuit are coupled to the memory cell in parallel,
the semiconductor memory device places the switching element of the memory cell from an OFF state to an ON state by applying a first voltage to the switching element of the memory cell by the first circuit and the second circuit,
the semiconductor memory device performs readout on the memory cell, the switching element of which is in the ON state, by applying a first current and a second voltage which is smaller than the first voltage to the switching element of the memory cell by the first circuit and without the second circuit, and
the OFF state is a state in which the switching element causes a current that is less than a second current to flow, and the ON state is a state in which the switching element causes a current that is equal to or more than the second current to flow, the second current being equal to or less than the first current.
2. The semiconductor memory device according to claim 1 , wherein the second circuit stops applying the first voltage before the readout is performed.
3. The semiconductor memory device according to claim 1 , wherein an applying time of the first voltage is shorter than a supplying time of the first current.
4. The semiconductor memory device according to claim 1 , wherein the first circuit repeats generation of the first current when it is determined that the memory cell is not in the ON state.
5. The semiconductor memory device according to claim 1 , wherein the switching element and the resistance change element are coupled in series, one end of the memory cell is coupled to the first circuit and the second circuit via the bit line, and the other end of the memory cell is coupled to a source line.
6. The semiconductor memory device according to claim 1 , wherein a third current that flows to the memory cell upon application of the first voltage differs from the first current.